published_or_final_version / Transport Policy and Planning / Master / Master of Arts in Transport Policy and Planning

For students and their families that live within the regional school system of Quebec, travel to school by bus has become a "fixed" activity. Households operate within a complex system of time, distance and accessibility constraints in adapting to the impact of this fixed bus schedule. This study focuses on the impact of this daily bus ride on the perceptions and behaviours of these households. The Household Activity-Travel Simulator (HATS) technique, developed at Oxford University, was adapted to a survey of 64 households in the Eastern Townships School Board of Quebec. Households were selected according to time-distance from the two English secondary schools in the region. The interview/survey solicited student and family responses and behaviours with respect to the daily bus trip. The study tests six related hypotheses on the effects of such large time units devoted to riding a bus. The hypotheses search for relationships between travel time and the daily activity schedules of students and their families. Through a number of quantitative and qualitative measures, the study concludes that the bus trip has an effect on students and, to a lesser degree, on their families.

Thesis (Ph. D.)--University of Montana, 2008. / Title from title screen. Description based on contents viewed May 4, 2009. Includes bibliographical references (p. 124-134).

Thesis (doctoral)--Universität Zürich.

Thesis (M.S.)--Rowan University, 2007. / Typescript. Includes bibliographical references.

Thesis (M.S.)--Rowan University, 2009. / Typescript. Includes bibliographical references.

Thesis (M.S.)--University of Alabama at Birmingham, 2008. / Title from PDF t.p. (viewed July 30, 2010). Includes bibliographical references (p. 51-52).

No description available.

Even with the performance of microprocessors expected to double within the next three to five years, the processing power increase offered by parallel processing has made multiprocessor systems very cost-effective. Each module in the multiprocessor systems will typically include a processor, coprocessor, cache, and main memory. This kind of architecture has generated the system-on-aboard distributed-intelligence concept, and the 32-bit multimaster buses thus come into play since these high-performance systems need to communicate with each other. During communication, commands and large blocks of data are transmitted across the bus. Along with the multiprocessor system, the single-CPU system continues to need a fast bus and wide data path to serve as a common I/O interface for terminals, disk storage devices, communication, and memory boards. With the board size limited, the trend toward distributed intelligence increases the need to place more functions on a single board, and therefore bus interface unit (BIU) integrated circuits (ICs) play an important role in the design of new boards. Spaceborn systems must be fault-tolerant due to their high susceptibility to transient faults and the high costs of repair and maintenance. Hence, a gate array fault-tolerant bus-interface IC based on modified NuBus protocols is designed to meet these requirements. The gate array IC design system HIGHLAND from United Technologies Microelectronics Center is used, along with other CAD tools such as the Berkeley VLSI Tool Set and LOGEN to generate a layout for the BIU. Two programs are written to interface the necessary CAD tools. All the circuits are designed and simulated on a VAXstation 3200 (Ultrix-32) and VAX11/785 (VMS). / Master of Science

No abstract available. / Thesis (M.Admin.)-University of Durban-Westville, 1991.