In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters. Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown. / Graduation date: 1999

High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997

The capacitor test process at ABB Capacitors in Ludvika must be improved to meet future demands for high voltage products. To find a solution to how to improve the test process, an investigation was performed to establish which parts of the process are used and how they operate. Several parts which can improves the process were identified. One of them was selected to be improved in correlation with the subject, mechanical engineering. Four concepts were generated and decision matrixes were used to systematically select the best concept. By improving the process several benefits has been added to the process. More units are able to be tested and lead time is reduced. As the lead time is reduced the cost for each unit is reduced, workers will work less hours for the same amount of tested units, future work to further improve the process is also identified. The selected concept was concept 1, the sway stop concept. This concept is used to reduce the sway of the capacitors as they have entered the test facility, the box. By improving this part of the test process a time saving of 20 seconds per unit can be achieved, equivalent to 7% time reduction. This can be compared to an additional 1400 units each year.

An electrochemical double-layer capacitor (EDLC) is a potential buffer for current power and energy supply. In this work, activated carbon derived from fluid coke as a brand new electrode material was studied due to its high specific surface area (SSA) and large portion of mesopores. A suitable electrode material formula, current collector, and cell configuration were investigated to fabricate a testable system and ensure the reproducibility of measurements. Cyclic voltammetry (CV) and constant current charge/discharge (CD) techniques were used to characterize the performance of the electrode material, as well as to study its fundamental behaviour. A new procedure was established for quantifying the capacitance (Cc) of EDLC from CV which isolates the effect of internal resistance on the measured capacitance (CM). The specific capacitance of single electrode made of activated carbon (~1900 m2/g) with approximately 80% mesopores and macropores was able to reach 180 F/g at scan rate of 0.5mV/s.

Multi-walled carbon nanotubes (MWCNTs) were successfully coated with two different pseudocapacitive polyoxometalates (POMs) (SiMo12O40-4 (SiMo12) and PMo12O40-3 (PMo12)) via “Layer-by-Layer” deposition. Even with merely a “single-layer” of POM, the modified nanotubes exhibited more than 2X increase in capacitance compared with that of bare nanotubes. To further improve their electrochemical performances, the deposition sequence of the POM layers was adjusted to form “alternate layer” coating to modify MWCNT. A synergistic effect on the capacitance and kinetics was observed with the alternate layer coatings. X-ray Photoelectron Spectroscopy (XPS) and Scanning Electron Microscopy (SEM) also proved the successful coating of POMs on MWCNTs. The potential-pH relationship provided important insights in terms of the deposition mechanism and suggested that the bottom layer close to the electrode substrate was the dominating layer in alternate layer coated MWCNT electrodes.

Multi-walled carbon nanotubes (MWCNTs) were successfully coated with two different pseudocapacitive polyoxometalates (POMs) (SiMo12O40-4 (SiMo12) and PMo12O40-3 (PMo12)) via “Layer-by-Layer” deposition. Even with merely a “single-layer” of POM, the modified nanotubes exhibited more than 2X increase in capacitance compared with that of bare nanotubes. To further improve their electrochemical performances, the deposition sequence of the POM layers was adjusted to form “alternate layer” coating to modify MWCNT. A synergistic effect on the capacitance and kinetics was observed with the alternate layer coatings. X-ray Photoelectron Spectroscopy (XPS) and Scanning Electron Microscopy (SEM) also proved the successful coating of POMs on MWCNTs. The potential-pH relationship provided important insights in terms of the deposition mechanism and suggested that the bottom layer close to the electrode substrate was the dominating layer in alternate layer coated MWCNT electrodes.

Power systems are protected by numerical relays that detect and isolate faults that may occur on power systems. The correct operation of the relay is very important to maintain the security of the power system. <p>Numerical relays that use voltage measurements from the power system provided by coupling capacitor voltage transformers (CCVT) have sometimes difficulty in correctly identifying a fault in the protected area. The fundamental frequency voltage phasor resulting from these CCVT measurements may result in a deviation from the true value and therefore may locate this phasor temporarily in the incorrect operating region. This phasor deviation is due to the CCVT behavior and the CCVT introduces spurious decaying and oscillating transient signal components on top of the original voltage received from the power system in response to sudden voltage changes produced during faults. Most of the existing methods for estimating the voltage phasor do not take advantage of the knowledge of the CCVT behavior that can be obtained from its design parameters.<p>A new least squares error method for phasor estimation is presented in this thesis, which improves the accuracy and speed of convergence of the phasors obtained, using the knowledge of the CCVT behavior. The characteristics of the transient signal components introduced by the CCVT, such as frequencies and time constants of decay, are included in the description of the curve to be fitted, which is required in a least squares fitting technique. Parameters such as window size and sampling rate for optimum results are discussed.<p>The method proposed is evaluated using typical power systems, with results that can be compared to the response if an ideal potential transformer (PT) were used instead of a CCVT. The limitations of this method are found in some specific power system scenarios, where the natural frequencies of the power system are close to that of the CCVT, but with longer time constants. The accuracy with which the CCVT parameters are known is also assessed, with results that show little impact compared to the improvements achievable.

The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher and higher performance from the hardware components in many communication and multimedia systems, but at the same time increased mobility demands less and less power consumption. Many applications, such as instrumentation, video, radar and communications, require very high accuracy and speed and with resolutions up to 16 bits and sampling rates in the 100s of MHz, pipelined ADCs are very suitable for such purposes. Resolutions above 10 bits often require very high power consumption and silicon area if no error correction technique is employed. Calibration relaxes the accuracy requirement of the individual building blocks of the ADC and enables power and area savings. Digital calibration is preferred over analog calibration due to higher robustness and accuracy. Furthermore, the microprocessors that process the digital information from the ADCs have constantly reduced cost and power consumption and improved performance due to technology scaling and innovative microprocessor architectures. The work in this dissertation presents a novel digital background calibration technique for high-speed, high-resolution pipelined ADCs. The technique is implemented in a 14 bit, 100 MS/s pipelined ADC fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.13µm Complementary Metal Oxide Semiconductor (CMOS) digital technology. The prototype ADC achieves better than 11.5 bits linearity at 100 MS/s and achieves a best-in-class figure of merit of 360 fJ/conversion-step. The core ADC has a power consumption of 105 mW and occupies an active area of 1.25 mm^2. The work in this dissertation also presents a low-power, 8-bit algorithmic ADC. This ADC reduces power consumption at system level by minimizing voltage reference generation and ADC input capacitance. This ADC is implemented in International Business Machines Corporation (IBM) 90nm digital CMOS technology and achieves around 7.5 bits linearity at 0.25 MS/s with a power consumption of 300 µW and an active area of 0.27 mm^2.

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

An electrochemical double-layer capacitor (EDLC) is a potential buffer for current power and energy supply. In this work, activated carbon derived from fluid coke as a brand new electrode material was studied due to its high specific surface area (SSA) and large portion of mesopores. A suitable electrode material formula, current collector, and cell configuration were investigated to fabricate a testable system and ensure the reproducibility of measurements. Cyclic voltammetry (CV) and constant current charge/discharge (CD) techniques were used to characterize the performance of the electrode material, as well as to study its fundamental behaviour. A new procedure was established for quantifying the capacitance (Cc) of EDLC from CV which isolates the effect of internal resistance on the measured capacitance (CM). The specific capacitance of single electrode made of activated carbon (~1900 m2/g) with approximately 80% mesopores and macropores was able to reach 180 F/g at scan rate of 0.5mV/s.