Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Polymers are very attractive materials that can be tailored for specific needs and functionalities. Based on their chemical structure, they can for instance be made electrically insulating or semiconducting with specific mechanical properties. Polymers are often processable from a solution, which enables the use of conventional low-cost and high-volume manufacturing techniques to print electronic devices onto flexible substrates. A multitude of polymer-based electronic and electrochemical devices and sensors have been developed, of which some already has reached the consumer market. This thesis focuses on polarization characteristics in polyelectrolyte-based capacitor structures and their role in sensors, transistors and supercapacitors. The fate of the ions in these capacitor structures, within the polyelectrolyte and at the interfaces between the polyelectrolyte and various electronic conductors (a metal, a semiconducting polymer or a network of carbon nanotubes), is of outermost importance for the device function. The humidity-dependent polarization characteristics in a polyelectrolyte capacitor are used as the sensing probe for wireless readout of a passively operated humidity sensor circuit. This sensor circuit can be integrated into a printable low-cost passive sensor label. By varying the humidity level, limitations and possibilities are identified for polyelectrolyte-gated organic field-effect transistors. Further, the effect of the ionic conductivity is investigated for polyelectrolyte-based supercapacitors. Finally, by using an ordinary electrolyte instead of a polyelectrolyte and a high-surface area (supercapacitor) gate electrode, the device mechanisms proposed for electrolyte-gated organic transistors are unified.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Power systems are protected by numerical relays that detect and isolate faults that may occur on power systems. The correct operation of the relay is very important to maintain the security of the power system. <p>Numerical relays that use voltage measurements from the power system provided by coupling capacitor voltage transformers (CCVT) have sometimes difficulty in correctly identifying a fault in the protected area. The fundamental frequency voltage phasor resulting from these CCVT measurements may result in a deviation from the true value and therefore may locate this phasor temporarily in the incorrect operating region. This phasor deviation is due to the CCVT behavior and the CCVT introduces spurious decaying and oscillating transient signal components on top of the original voltage received from the power system in response to sudden voltage changes produced during faults. Most of the existing methods for estimating the voltage phasor do not take advantage of the knowledge of the CCVT behavior that can be obtained from its design parameters.<p>A new least squares error method for phasor estimation is presented in this thesis, which improves the accuracy and speed of convergence of the phasors obtained, using the knowledge of the CCVT behavior. The characteristics of the transient signal components introduced by the CCVT, such as frequencies and time constants of decay, are included in the description of the curve to be fitted, which is required in a least squares fitting technique. Parameters such as window size and sampling rate for optimum results are discussed.<p>The method proposed is evaluated using typical power systems, with results that can be compared to the response if an ideal potential transformer (PT) were used instead of a CCVT. The limitations of this method are found in some specific power system scenarios, where the natural frequencies of the power system are close to that of the CCVT, but with longer time constants. The accuracy with which the CCVT parameters are known is also assessed, with results that show little impact compared to the improvements achievable.

The operation speed of power delivery system of packages has been upgraded to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power plane and the ground plane, then to produce the programs of electromagnetic interference. In this thesis, we will analyze the EMI of power delivery system of packages by finite-difference time-domain in two dimensions structure in three sections. In firist section, to computing EMI in finite-difference time-domain in two dimensions structure. In second section, to analyze more complicated power delivery plane, ex: EBG, in finite-difference time-domain in two dimensions structure. In three section, to add property of capacitors on power plane to reduce EMI in two dimensions structure. Above all, we hope to built a fast computing method to compute EMI to solve the time-consuming problems of full-wave simulated software. And to supply the engineer to deal with the similar problems in packages efficiently.

The trend toward higher-level circuit integration is the result of demand for lower cost and smaller feature size. The goal of this trend is to have a single-chip solution, in which analog and digital circuits are placed on the same die with advanced CMOS technology. The complete integration of a system may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. Although advanced fabrication technology benefits digital circuits, it poses great challenges for analog circuits. For instance, the scaling of CMOS devices degrades important analog performance such as output resistance, lowering amplifier gain. Simply lowering the power supply voltage in analog circuits does not necessarily result in lower power dissipation. The many design constraints common to the design of analog circuits makes it difficult to curb their power consumption. This is especially true for already complicated analog systems like ADCs; reducing their appetite for power requires careful analysis of system requirements and special strategies. This thesis describes a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers and so on. The ADC is designed in a 90nm CMOS technology with a 1.2V supply voltage.

This paper presents a distributed feedback and feedforward of discrete-time delta sigma modulator applications in the radio. We know the delta-sigma modulator using oversampling and noise shaping technique, thus we can relax the specifications of the components. This paper described the architectural differences and compare, the in-band signal is less sensitive to noise interference, and improve the resolution of the circuit. In the resonator, a simple structure with a small number of capacitor in resonator circuit. This paper uses the TSMC 0.18£gm process parameters to the simulation, implementation, and measurement. Our fourth-order discrete-time delta-sigma modulator specifications as follows: the input signal frequency is 10.7MHz, the sampling frequency is 42.8MHz, the signal bandwidth is 200kHz, oversampling rate is 107, and one bit quantizer.

Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load. This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load.

In recent high-speed digital circuits with pico-second rising/falling edges, it is reasonable to consider the power/ground planes as a dynamic electromagnetic system. The simultaneous switching noise (SSN) or ground bounce noise (GBN), resulting from the transient currents which flow between power/ground planes during the state transitions of the logic gates, has become a critical factor to degrade the signal integrity (SI) and power integrity (PI) in PCB or package design. In order to accurately perform overall system-level power integrity simulation, extracting the SPICE-compatible models with the resonant effect being considered in the power/ground planes and incorporating the model into the conventional circuit simulator, such as SPICE, is essential. In this thesis, a two-dimensional transmission line (2D-TL) model is proposed for constructing the SPICE-compatible model of the power/ground planes. Based on this model, the ground bounce noise for the BGA package mounted on a PCB can be efficiently evaluated. It is found that the behavior of GBN between the only package and package mounted on a PCB (hybrid structure) is obvious different. Then, we combine the SPICE-compatible model of the power/ground planes with decoupling capacitors to fast evaluate the behavior of GBN. It also has a good agreement between our model and the measured result. Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequency higher than GHz due to their inherent lead inductance. In recent, a new method for eliminating the GBN at higher frequency is proposed by electromagnetic bandgap (EBG) structure with high impedance surface (HIS). Finally, we utilize 2D-TL model to fast analyze the behavior of the EBG, and combine decoupling capacitors with EBG structure to research the suppression of the GBN.

This thesis includes the study of hybrid microwave integrated circuits (HMIC), miniaturization techniques applied on HMICs and its application on a frequency modulated continuous wave (FMCW) range sensor transceiver. In the scope of study, hybrid and monolithic microwave integrated circuits (HMIC and MMIC) are introduced, advantages and disadvantages of these two types are discussed. Large size of HMICs is the main disadvantage especially for military and civil applications requiring miniature volumes. This thesis is mainly devoted on miniaturization work of HMICs in order to cope with this problem. In this scope, miniaturization techniques of some HMICs such as 3 dB hybrid couplers and stubs are examined and analyzed. Their simulation and measurement results cohere with original circuit results. Nevertheless, considerable size reduction up to 80% is achieved. Moreover, planar interdigital capacitors (IDC), spiral inductors (SI) and their equivalent circuit models are introduced. Design technique is discussed with illustrative electromagnetic (EM) simulations. Furthermore, FMCW radar is introduced with its basic operation principles, brief history and usage areas. In addition, FMCW range sensor transceiver is designed with its sub&amp / #8208 / parts / power amplifier, low noise amplifier (LNA), coupler and front end. Multi technology based on chip transistors, interdigital capacitors, spiral inductors and hybrid couplers with wire&amp / #8208 / bond connections is used in the design. As the result of using hybrid miniaturized components small layout size is achieved for the transceiver system with its all components.