CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior / Este trabalho apresenta o estudo, o projeto e a implementaÃÃo de um driver trifÃsico para diodos emissores de luz (LEDs) baseado num conversor com capacitor chaveado (SC â Switched Capacitor), tambÃm conhecido como charge-pump. Uma luminÃria LED com a tecnologia Chip-on-Board (COB), que proporciona uma elevada densidade de potÃncia, à utilizada como carga. Assim como os LEDs, os drivers destes dispositivos devem apresentar uma longa vida Ãtil e um elevado rendimento. A vida Ãtil dos drivers para LEDs à geralmente limitada pelo uso de capacitores eletrolÃticos convencionais. Estes dispositivos apresentam uma vida Ãtil incompatÃvel com a dos LEDs e, por isso, nÃo devem ser utilizados nos seus drivers. AlÃm disso, os drivers para LEDs devem proporcionar uma baixa ondulaÃÃo de corrente nos LEDs, garantindo um baixo flicker percentual e evitando danos à saÃde humana. Diante destes problemas, o conversor trifÃsico SC proposto nÃo utiliza capacitores eletrolÃticos, o que eleva a expectativa de vida Ãtil do driver. O conversor emite um baixo flicker percentual e à capaz de estabilizar a corrente de saÃda sem a necessidade de um controle de malha fechada, o que pode reduzir os custos de projeto. A topologia permite a dimerizaÃÃo dos LEDs atravÃs da variaÃÃo da frequÃncia de comutaÃÃo. Resultados experimentais de um protÃtipo de 216 W sÃo analisados e discutidos para validaÃÃo da proposta. Em condiÃÃes nominais, o conversor apresentou um rendimento global de 91,5%, um fator de potÃncia acima de 0,99 e uma distorÃÃo harmÃnica menor que 5% nas trÃs fases, obedecendo as Classes A e C da norma IEC 61000-3-2:2014. AlÃm disso, foi obtida uma ondulaÃÃo de corrente de alta frequÃncia igual a 16,97% e um flicker percentual de 4,97%, estando de acordo com as recomendaÃÃes da IEEE. A dimerizaÃÃo dos LEDs permitiu a reduÃÃo da potÃncia de saÃda em atà 50%, com rendimento prÃximo a 91%, fator de potÃncia acima de 0,97, distorÃÃo harmÃnica total inferior a 6% para as trÃs fases e flicker percentual menor que 7% para toda a faixa de potÃncia. / This paper presents the study, design and implementation of a three-phase light-emitting diode (LED) driver based on a switched capacitor (SC) converter, also known as charge-pump. A LED lamp with Chip-On-Board (COB) technology, which provides a high power density, is used as load. As the LEDs, drivers of these devices must have a high efficiency and a long useful lifetime, which is usually limited by the use of conventional electrolytic capacitors. These devices have an incompatible lifetime with LEDs and, therefore, they should not be used in their drivers. In addition, the LED drivers should provide a low ripple current in LEDs, which can provide the emission of a low percent flicker. Studies demonstrate that excessive percent flicker may cause damage to human health. Given these problems, the proposed switched capacitor LED driver does not use electrolytic capacitors, which increases the expectative of useful lifetime of the driver. It emits a low percent flicker, which reduces the risks to human health. It can stabilize the output current without the need of a closed-loop control, which may reduce design costs. It allows the LEDs dimming by varying the switching frequency. An experimental prototype rated at 216 W has been developed in order to evaluate the performance of the proposed approach, while results are properly presented and discussed. In nominal conditions, the drive presented an overall efficiency of 91.5%, a power factor greater than 0.99 and a current total harmonic distortion lower than 5% in three phases. The harmonic currents are in accordance with the limits imposed by IEC Standard 61000-3-2:2014 to class A and C equipment. Furthermore, a high frequency current ripple equal to 16.97% and a percent flicker of 4.97% was obtained, which is in accordance with IEEE recommendations. The LEDs dimming allowed the reduction of the output power up to 50%, while the efficiency remained close to 91% and the power factor remained above 0.97. In addition, the total harmonic distortion was below 6% and the percent flicker was lower than 7% for the entire dimming range.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date.

Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date.

Made available in DSpace on 2014-12-17T14:06:57Z (GMT). No. of bitstreams: 1 SamuelNC_DISSERT.pdf: 3182728 bytes, checksum: 8bfe4bb2137c514846453d3aeb267c09 (MD5) Previous issue date: 2012-05-11 / Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico / It seeks to find an alternative to the current tantalum electrolytic capacitors in the market due to its high cost. Niobium is a potential substitute, since both belong to the same group of the periodic table and because of this have many similar physical and chemical properties. Niobium has several technologically important applications, and Brazil has the largest reserves, around 96%. There are including niobium in reserves of tantalite and columbite in Rio Grande do Norte. These electrolytic capacitors have high capacitance specifies, ie they can store high energy in small volumes compared to other types of capacitors. This is the main attraction of this type of capacitor because is growing demand in the production of capacitors with capacitance specifies increasingly high, this because of the miniaturization of various devices such as GPS devices, televisions, computers, phones and many others. The production route of the capacitor was made by powder metallurgy. The initial niobium powder supplied by EEL-USP was first characterized by XRD, SEM, XRF and laser particle size, to then be sieved into three particle size, 200, 400 e 635mesh. The powders were then compacted and sintered at 1350, 1450 and 1550?C using two sintering time 30 and 60min. Sintering is one of the most important parts of the process as it affects properties as porosity and surface cleaning of the samples, which greatly affected the quality of the capacitor. The sintered samples then underwent a process of anodic oxidation, which created a thin film of niobium pent?xido over the whole porous surface of the sample, this film is the dielectric capacitor. The oxidation process variables influence the performance of the film and therefore the capacitor. The samples were characterized by electrical measurements of capacitance, loss factor, ESR, relative density, porosity and surface area. After the characterizations was made an annealing in air ate 260?C for 60min. After this treatment were made again the electrical measurements. The particle size of powders and sintering affected the porosity and in turn the specific area of the samples. The larger de area of the capacitor, greater is the capacitance. The powder showed the highest capacitance was with the smallest particle size. Higher temperatures and times of sintering caused samples with smaller surface area, but on the other hand the cleaning surface impurities was higher for this cases. So a balance must be made between the gain that is achieved with the cleaning of impurities and the loss with the decreased in specific area. The best results were obtained for the temperature of 1450?C/60min. The influence of annealing on the loss factor and ESR did not follow a well-defined pattern, because their values increased in some cases and decreased in others. The most interesting results due to heat treatment were with respect to capacitance, which showed an increase for all samples after treatment / Procura-se encontrar uma alternativa para os atuais capacitores eletrol?ticos de t?ntalo existentes no mercado, devido ao seu alto custo. O ni?bio ? um substituto em potencial, pois ambos pertencem ao mesmo grupo da tabela peri?dica e devido a isso t?m v?rias propriedades f?sicas e qu?micas semelhantes. O ni?bio apresenta diversas aplica??es tecnologicamente importantes e o Brasil possui as maiores reservas mundiais, em torno de 96%. Existe inclusive ni?bio contido em reservas de tantalita e columbita no Rio Grande do Norte. Esses capacitores eletrol?ticos possuem alta capacit?ncia especifica, ou seja, podem armazenar altas energias em volumes pequenos comparados a outros tipos de capacitores. Esse ? o principal atrativo desse tipo de capacitores, pois existe uma crescente demanda na produ??o de capacitores com capacit?ncia especifica cada vez mais alta, isso devido ? miniaturiza??o de diversos aparelhos como GPSs, televisores, computadores, celulares e muitos outros. A rota de produ??o do capacitor foi feita atrav?s da metalurgia do p?. O p? de ni?bio inicial fornecido pela EEL-USP foi primeiramente caracterizado atrav?s de DRX, MEV, granulometria a laser e FRX, para ent?o ser peneirado em tr?s granulometrias, 200, 400 e 635mesh. Os p?s foram ent?o compactados e sinterizados em 1350, 1450 e 1550?C usando dois patamares, 30 e 60min. A sinteriza??o ? uma das partes mais importantes do processo, pois afeta propriedades como porosidade e limpeza superficial das amostras, que afetaram grandemente a qualidade do capacitor. As amostras sinterizadas sofreram ent?o um processo de oxida??o an?dica, que criou um filme fino de pent?xido de ni?bio sobre toda a superf?cie porosa da amostra, este filme ? o diel?trico do capacitor. As vari?veis do processo de oxida??o influenciaram no desempenho do filme e conseq?entemente do capacitor. As amostras foram caracterizadas atrav?s de medidas el?tricas de capacit?ncia, fator de perdas, ESR, densidade relativa, porosidade e ?rea superficial. Ap?s as caracteriza??es foi feito um tratamento t?rmico de recozimento em atmosfera de ar a 260?C por 60min. Ap?s esse tratamento foram feitas novamente as medidas el?tricas. A granulometria do p? e a sinteriza??o afetaram a porosidade e por sua vez a ?rea especifica das amostras. Quanto maior a ?rea do capacitor, maior sua capacit?ncia. O p? que apresentou capacit?ncia mais alta foi o com menor granulometria. Temperaturas e tempos de sinteriza??o maiores causaram amostras com ?rea superficial menores, por?m, por outro lado a limpeza superficial de impurezas foi maior para esses casos, de maneira que deve ser feito um balanceamento entre o ganho que se obt?m com a limpeza das impurezas e a perda com a diminui??o da ?rea especifica. Os melhores resultados foram obtidos para a temperatura de 1450?C/60min. A influ?ncia do tratamento t?rmico de recozimento no fator de perdas e na ESR n?o seguiu um padr?o bem definido, pois seus valores aumentaram em alguns casos e diminu?ram em outros. Os resultados mais interessantes devido ao tratamento t?rmico foram com rela??o ? capacit?ncia, que apresentou um aumento para todas as amostras ap?s o tratamento

Made available in DSpace on 2014-12-17T14:54:51Z (GMT). No. of bitstreams: 1 MaxCPF.pdf: 2292044 bytes, checksum: 061617ed85fc5d1b1a73b816f160aedb (MD5) Previous issue date: 2005-10-21 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / The usual programs for load flow calculation were in general developped aiming the simulation of electric energy transmission, subtransmission and distribution systems. However, the mathematical methods and algorithms used by the formulations were based, in majority, just on the characteristics of the transmittion systems, which were the main concern focus of engineers and researchers. Though, the physical characteristics of these systems are quite different from the distribution ones. In the transmission systems, the voltage levels are high and the lines are generally very long. These aspects contribute the capacitive and inductive effects that appear in the system to have a considerable influence in the values of the interest quantities, reason why they should be taken into consideration. Still in the transmission systems, the loads have a macro nature, as for example, cities, neiborhoods, or big industries. These loads are, generally, practically balanced, what reduces the necessity of utilization of three-phase methodology for the load flow calculation. Distribution systems, on the other hand, present different characteristics: the voltage levels are small in comparison to the transmission ones. This almost annul the capacitive effects of the lines. The loads are, in this case, transformers, in whose secondaries are connected small consumers, in a sort of times, mono-phase ones, so that the probability of finding an unbalanced circuit is high. This way, the utilization of three-phase methodologies assumes an important dimension. Besides, equipments like voltage regulators, that use simultaneously the concepts of phase and line voltage in their functioning, need a three-phase methodology, in order to allow the simulation of their real behavior. For the exposed reasons, initially was developped, in the scope of this work, a method for three-phase load flow calculation in order to simulate the steady-state behaviour of distribution systems. Aiming to achieve this goal, the Power Summation Algorithm was used, as a base for developing the three phase method. This algorithm was already widely tested and approved by researchers and engineers in the simulation of radial electric energy distribution systems, mainly for single-phase representation. By our formulation, lines are modeled in three-phase circuits, considering the magnetic coupling between the phases; but the earth effect is considered through the Carson reduction. It s important to point out that, in spite of the loads being normally connected to the transformer s secondaries, was considered the hypothesis of existence of star or delta loads connected to the primary circuit. To perform the simulation of voltage regulators, a new model was utilized, allowing the simulation of various types of configurations, according to their real functioning. Finally, was considered the possibility of representation of switches with current measuring in various points of the feeder. The loads are adjusted during the iteractive process, in order to match the current in each switch, converging to the measured value specified by the input data. In a second stage of the work, sensibility parameters were derived taking as base the described load flow, with the objective of suporting further optimization processes. This parameters are found by calculating of the partial derivatives of a variable in respect to another, in general, voltages, losses and reactive powers. After describing the calculation of the sensibility parameters, the Gradient Method was presented, using these parameters to optimize an objective function, that will be defined for each type of study. The first one refers to the reduction of technical losses in a medium voltage feeder, through the installation of capacitor banks; the second one refers to the problem of correction of voltage profile, through the instalation of capacitor banks or voltage regulators. In case of the losses reduction will be considered, as objective function, the sum of the losses in all the parts of the system. To the correction of the voltage profile, the objective function will be the sum of the square voltage deviations in each node, in respect to the rated voltage. In the end of the work, results of application of the described methods in some feeders are presented, aiming to give insight about their performance and acuity / Os programas desenvolvidos para o c?lculo de fluxo de carga sempre foram amplamente utilizados objetivando simular sistemas de transmiss?o, subtransmiss?o e distribui??o de energia el?trica. Entretanto, os m?todos matem?ticos aplicados para esse c?lculo estruturavam-se, em sua maioria, tomando como base apenas as caracter?sticas dos sistemas de transmiss?o, os quais eram o principal foco de preocupa??o dos engenheiros e pesquisadores. Todavia, as caracter?sticas f?sicas desses sistemas s?o bastante diferentes da realidade dos de distribui??o. Nos sistemas de transmiss?o, os n?veis de tens?o s?o altos e as linhas s?o geralmente muito longas. Esses fatores contribuem para que os efeitos capacitivos e indutivos que aparecem nos sistemas passem a ter uma influ?ncia consider?vel nos valores das grandezas de interesse, raz?o por que devem ser considerados. Ainda nos sistemas de transmiss?o, as cargas s?o de natureza macro, a exemplo de cidades, bairros, ou grandes ind?strias ou consumidores. Tais cargas s?o, em geral, praticamente equilibradas, o que reduz a necessidade de utiliza??o de metodologias trif?sicas para o c?lculo do fluxo. Os sistemas de distribui??o, por sua vez, pressup?em outras implica??es, apesar de os n?veis de tens?o serem pequenos em compara??o aos de transmiss?o, o que praticamente anula o efeito capacitivo das linhas. Como as cargas passam a ser, neste caso, transformadores, em cujos secund?rios est?o conectados pequenos consumidores, muitas vezes, monof?sicos, a possibilidade de se encontrar um circuito desbalanceado ? grande. Portanto, face a tal possibilidade, a utiliza??o de metodologias trif?sicas assume uma dimens?o importante. Al?m disso, equipamentos como reguladores de tens?o, para cujo funcionamento utilizam simultaneamente o conceito de tens?o de fase e de linha, necessitam de uma metodologia trif?sica, para que seu modelo permita simula??o em tempo real. Pelas raz?es expostas, o trabalho apresenta um m?todo de c?lculo de fluxo de carga trif?sico para sistemas de distribui??o de energia. No intuito de realizar tal tarefa, foi utilizado como base o m?todo Soma de Pot?ncias, j? bastante testado e aprovado na simula??o de sistemas radiais de distribui??o de energia el?trica. As linhas s?o a tr?s fios, considerando-se o acoplamento magn?tico entre as fases; j? o efeito da terra foi considerado atrav?s da corre??o de Carson. ? interessante ressaltar que, apesar de as cargas estarem normalmente conectadas nos secund?rios dos transformadores, foi considerada, al?m dessa possibilidade, a hip?tese da exist?ncia de cargas em estrela ou delta no circuito prim?rio. J? para a simula??o de reguladores de tens?o, foi utilizado um novo modelo que permite a simula??o dos v?rios tipos de configura??es, de acordo com o seu funcionamento real. Por fim, tamb?m foi considerada a possibilidade da representa??o com chaves de medi??o de corrente em diversos pontos do alimentador. As cargas s?o ajustadas, durante o processo iterativo, de maneira que a corrente em cada chave convirja para o valor especificado nos dados de entrada. Em uma segunda etapa, tomando como base o fluxo de carga descrito, o trabalho apresenta um m?todo de c?lculo para os par?metros de sensibilidade, com o objetivo de serem aplicados em processos de otimiza??o. Esses par?metros s?o encontrados atrav?s do c?lculo da derivada parcial de uma vari?vel com rela??o a uma outra, determinando a taxa de varia??o entre elas. Ap?s a descri??o de c?lculo dos par?metros de sensibilidade, apresenta-se o m?todo do gradiente, que usa esses par?metros para determinar o ponto ?timo de uma fun??o objetivo, que ser? definida para cada tipo de estudo. Neste trabalho s?o abordados dois tipos de problema. O primeiro refere-se ? redu??o das perdas t?cnicas em um alimentador de m?dia tens?o, atrav?s da instala??o de bancos de capacitores; o segundo trata do problema da corre??o do perfil de tens?o, atrav?s da instala??o de bancos de capacitores ou de reguladores de tens?o. No caso da redu??o das perdas ser? considerada, como fun??o objetivo, a soma das perdas em todos os trechos do sistema. J? para a corre??o do perfil de tens?o, a fun??o objetivo ser? a soma do quadrado dos desvios de tens?o em cada n?, com rela??o ? tens?o requerida. No final do trabalho, os m?todos descritos foram aplicados em alguns alimentadores com a finalidade de testar o seu desempenho e precis?o

[pt] Após a incidência de inúmeros colapsos ocorridos nos sistemas de transmissão de energia devido ao uso extremo das linhas de transmissão, a estabilidade, ou mais adequadamente, a segurança de tensão tornou-se um assunto importante os últimos anos. A correta representação de cargas e de dispositivos de controle de tensão é cada vez mais importante na análise de segurança de tensão do sistema elétrico, em função da sua complexidade crescente e da necessidade de ações operativas mais precisas. A avaliação das condições de segurança de tensão é realizada com base em um modelo linearizado das equações de fluxo de carga, incluindo toda e qualquer equação de controle, e os índices resultantes são calculados a partir de um determinado ponto de operação. Em estudos off-line, este ponto é usualmente proveniente do resultado de um problema de fluxo de carga. É importante que os modelos matemáticos do sistema e seus componentes, de controles e de limites sejam compatíveis nos dois programas computacionais. Estuda-se neste trabalho a modelagem em regime permanente, e a incorporação à função de avaliação da segurança de tensão, de cargas do tipo motor de indução e do controle de tensão por faixa através de capacitores chaveáveis. Aspectos fundamentais da presença de motores de indução e capacitores chaveáveis na avaliação da segurança de tensão são apresentados e discutidos. São mostrados exemplos numéricos de avaliação dos índices de estabilidade de tensão que ilustram a necessidade de uma modelagem realista. / [en] After the incidence of innumerable collapses occurred in the energy transmission systems due to the extreme use of the transmission lines, the voltage stability, or more adequately, the voltage security became an important issue in the last years. The correct representation of loads and voltage control devices is important in the analysis of voltage security of the electrical system, due to its increasing complexity and to the necessity of more accurate and secure operative actions. The voltage security assessment is based on a linear model of the load flow equations, including all and any control equation, and the resulting indexes are calculated for a specified operating point. In off-line studies the operating point is usually obtained from a load flow algorithm. It is important that the system and its components mathematical models, control devices and limits are compatible in both computational programs. This work is concerned with the steady state modelling and its incorporation into the voltage security assessment function, of induction motor type loads and band voltage control by switchable capacitors. Fundamental aspects of induction motors and switchable capacitors in the assessment of voltage security are presented and discussed. Numerical examples of voltage stability assessment indexes are presented to illustrate the necessity of realistic modelling.

The advances in modern communication systems have brought about devices with more functionality, better performance, smaller size, lighter weight and lower cost. Meanwhile, the requirement for newer devices has become more demanding than ever. Tunability and flexibility are both long-desired features. Tunable devices are ‘smart’ in the sense that they can adapt to the dynamic environment or varying user demand as well as correct the minor deviations due to manufacturing fluctuations, therefore making it possible to reduce system complexity and overall cost. It is also desired that electronics be flexible to provide conformability and portability. Previously, tunable devices on flexible substrates have been realized mainly by dicing and assembling. This approach is straightforward and easy to carry out. However, it will become a “mission impossible” when it comes to assembling a large amount of rigid devices on a flexible substrate. Moreover, the operating frequency is often limited by the parasitic effect of the interconnection between the diced device and the rest of the circuit on the flexible substrate. A recent effort utilized a strain-sharing Si/SiGe/Si nanomembrane to transfer a device onto a flexible substrate. This approach works very well for silicon based devices with small dimensions, such as transistors and varactor diodes. Large-scale fabrication capability is still under investigation. A new transfer technique is proposed and studied in this research. Tunable BST (Barium Strontium Titanate) IDCs (inter-digital capacitors) are first fabricated on a silicon substrate. The devices are then transferred onto a flexible LCP (liquid crystalline polymer) substrate using iv wafer bonding of the silicon substrate to the LCP substrate, followed by silicon etching. This approach allows for monolithic fabrication so that the transferred devices can operate in millimeter wave frequency. The tunability, capacitance, Q factor and equivalent circuit are studied. The simulated and measured performances are compared. BST capacitors on LCP substrates are also compared with those on sapphire substrates to prove that this transfer process does not impair the performance. A primary study of a reflectarray antenna unit cell is also conducted for loss and phase swing performance. The BST thin film layout and bias line positions are studied in order to reduce the total loss. Transferring a full-size BST-based reflectarray antenna onto an LCP substrate is the ultimate goal, and this work is ongoing at the University of Central Florida (UCF). HFSS is used to simulate the devices and to prove the concept. All of the devices are fabricated in the clean room at UCF. Probe station measurements and waveguide measurements are performed on the capacitors and reflectarray antenna unit cells respectively. This work is the first comprehensive demonstration of this novel transfer technique.

No description available.