In order to meet the high demand for power transmission capacity, some power companies have installed series capacitors on power transmission lines. This allows the impedance of the line to be lowered, thus yielding increased transmission capability. The series capacitor makes sense because it's simple and could be installed for 15 to 30% of the cost of installing a new line, and it can provide the benefits of increased system stability, reduced system losses, and better voltage regulation.1 Protective distance relays, which make use of impedance measurements in order to determine the presence and location of faults, are "fooled" by installed series capacitance on the line when the presence or absence of the capacitor in the fault circuit is not known a priori. This is because the capacitance cancels or compensates some of the inductance of the line and therefore the relay may perceive a fault to be in its first zone when the fault is actually in the second or third zone of protection. Similarly, first zone faults can be perceived to be reverse faults! Clearly this can cause some costly operating errors. The general approach of interest is a method leading to the determination of the values of series L and C of the line at the time of the fault. This is done by analyzing the synchronous and subsynchronous content of the V and I signals seperately which provides adequate information to compute the series L and C of the line. / Master of Science

Master of Science / Department of Electrical Engineering / William B. Kuhn / During the development of an educational renewable energy production platform, it was found that there were no low-cost, efficient grid-tie interfaces for a 160 W DC wind turbine. Typically, a small DC wind turbine is used in conjunction with a rechargeable battery bank or, if the wind turbine is directly interfaced with a grid-tie inverter, a regulator with a diversion-load. The use of batteries is undesirable due to their high-cost and high-maintenance characteristics. Diversion loads by nature waste power, as any excess energy that cannot be accepted by a battery or inverter is usually converted into heat through a resistive element. Initially, a 24 V DC, 160 W Air Breeze small wind turbine was directly connected to an Enphase Energy M190 grid-tie micro-inverter. The 24 V DC Air Breeze wind turbine is designed to charge a battery or bank of batteries while the M190 micro-inverter is designed to convert the DC output of a 200 W solar panel to grid-tied AC power. As expected, the power-production response time associated with the small wind turbine and the power-accepting, load-matching response time of the micro-inverter were not compatible. The rapidly changing power output of the small wind turbine conflicted with the slow response time of the micro-inverter resulting in little power production. Ultimately, the response time mismatch also produced sufficiently large voltage spikes to damage the turbine electronics. In this thesis, a solution for a low-cost, efficient grid-tie interface using no batteries and no diversion load is presented. A capacitance of eight Farads is placed in parallel with the small wind turbine and the micro inverter. The large capacitance sufficiently smoothes the potential abrupt voltage changes produced by the wind turbine, allowing the micro-inverter adequate time to adjust its load for optimal power conversion. Laboratory experiments and data from an implementation of such a parallel super capacitor wind turbine to grid-tie micro-inverter configuration are provided along with DC and AC power production monitoring circuits interfaced with a micro controller.

Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical Engineering.

Recent portable electronic technologies require the power management circuit be efficient, small and cost effective. The switched-capacitor (SC) converter provides a trade-off between the efficiency, the size and the cost that is desirable in many of these new portable technologies. This dissertation investigates different circuit techniques and SC converter topologies to make the SC converters fully adapt to the portable system requirements. To make the SC converter efficient over a wide range of input and output voltages, a family of SC power stages with multiple gain ratio (GR) is developed. Multiple GR allows the converter to provide step-down or step-up voltage conversion while increasing the average efficiency of the converter. These power stages are also capable of providing interleaving regulation that has been proved to be effective in reducing the input and the output noise of the converter. Unlike conventional interleaving, the technique developed in this research uses fewer switches and capacitors. The research also contributes in developing circuit techniques such as charge recycling in the bottom plate parasitic capacitors, local gate driving and adaptive body biasing to reduce the power loss in monolithic SC converter implementation. To control the SC power stage for accurate regulation and fast transient response, a control scheme named adaptive gain/pulse control is developed. The research also investigates the use of multipath compensation scheme in SC converters for ultra fast and low noise performance. The techniques and the topologies developed for SC converters in this research can be effectively implemented in the portable devices to reduce cost, and improve efficiency which leads to longer battery life and circuit implementation using smaller areas.

Conveyors are an integral part of modern devices. In this thesis, a slew of areas oscillators and function generators with current and voltage conveyors. Individual applications are categorized according involvement with conveyors and other elements. The functionality of the need for involvement in the program PSpice simulation. As a current conveyor is used OPA861, EL2082, further use of RC circuits and opto-CNY 17.

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+. Os capacitores MOS com porta de Si-poli dopados com boro tiveram a estrutura Si-poli/SiO2/Si previamente implantada com nitrogênio nas doses de 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-², com o pico da concentração de nitrogênio próximo à interface SiO2/Si. Os capacitores MOS foram fabricados sobre lâminas de silício do tipo p que passaram por uma limpeza química préoxidação tipo RCA mais imersão final em solução diluída em HF. Na seqüência, as lâminas foram oxidadas em um ambiente de O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) que proporcionou óxidos de silício com excelentes características elétricas. Para a fabricação dos capacitores MOS com porta de Si-poli P+, utilizou-se SOG de boro seguido por difusão térmica sobre camada de Si-poli (340 nm). Após testes com receitas de difusão a 950, 1000, 1050 e 1100 °C todas padronizadas por um tempo de 30 min optamos por realizar a difusão a 1050 °C por 30 min, pois essa receita proporcionou concentração de boro superior a 1.10\'POT.20\' at.cm-³ e segregação desprezível do boro em direção ao substrato de Si. A dopagem dos capacitores MOS com porta de Si-poli N+ foi realizada por aplicação do SOG de fósforo seguido por difusão a 1050 °C por 30 min. Os resultados indicaram segregação do boro desprezível para o Si, baixa densidade de estados de interface (< 1.10\'POT.11\' eV-¹ cm-²) e no aumento do campo elétrico de ruptura (de 14 MV/cm para 21 MV/cm) com o aumento da dose de nitrogênio (de 1.10\'POT.13\' a 5.10\'POT.15\' at/cm²). Embora ocorresse uma maior dispersão e um aumento desfavorável da tensão de banda plana com o aumento da dose de nitrogênio, os valores 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-² resultaram em capacitores MOS com tensão de faixa plana próxima ao parâmetro diferença de função trabalho (\'fi\' MS) significando densidade efetiva de cargas no dielétrico de porta inferior à cerca de 1.10\'POT.11\' cm-². / In this work we manufactured and electrically characterized MOS capacitors with ultrathin silicon oxides (2,6 nm) and polysilicon gate (Si-poli), P+ or N+. P+ - doped polysilicon gate MOS capacitors (Si-poli/SiO2/Si structure) were previously implanted with nitrogen using doses of 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-², and implantation peak centered close to the SiO2/Si interface before boron doping. The MOS capacitors were fabricated on p-type silicon wafers, which were submitted to RCA - based cleaning procedure and a final dip in diluted HF solution. Following, the wafers were oxidize in ultrapure O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) having, as a result, silicon gate oxides with excellent electrical characteristics. To obtain P+ polysilicon, it Spin On Glass (SOG) of boron the wafers was annealed at 950, 1000, 1050 or 1100 °C during 30 min. We have chosen a diffusion recipe of 1050 °C during 30 min to obtain volumetric concentration of boron higher than 1.10\'POT.20\' cm-³ and no boron segregation to the silicon. N+ polysilicon was also obtained using phosphorus SOG and diffusion at 1050 °C during 30 min. As a result, besides no boron segregation to Si, the interface states density was low (< 1.10\'POT.11\' eV-¹cm-²) and the breakdown field of the gate oxides increased (from 14 MV/cm to 21 MV/cm) by increasing the nitrogen doses (from 1.10\'POT.13\' to 5.10\'POT.15\' at/cm²). Although a larger dispersion and increasing of the flat-band voltage have occurred as the nitrogen dose was increased, values of 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-² induced flat band voltage close to the parameter workfunction difference (\'fi\'MS) which meant effective charge density in the gate dielectrics lower than about 1.10\'POT.11\' cm-².

Este trabalho apresenta um conversor CC - CC baseado em Capacitores Chaveados de 6 fases e tempos intercalados com o objetivo de coletar energia fotovoltaica projetado em tecnologia CMOS de 130 nm para ser usado em aplicações em Internet das Coisas e Nós Sensores. Ele rastreia o máximo ponto de entrega de energia de um painel fotovoltaico policristalino de 3 cm x 3 cm através de modulação da frequência de chaveamento com o objetivo de carregar baterias. A razão da tensão de circuito aberto foi a estratégia de rastreio escolhida. O conversor foi projetado em uma tecnologia CMOS de 130 nm e alcança uma eficiência de 90 % para potencias de entrada maiores do que 30 mW e pode operar com tensões que vão de 1.25 até 1.8 V, resultando em saídas que vão de 2.5 até 3.6, respectivamente. Os circuitos periféricos também incluem uma proteção contra sobre tensão na saída de 3.6 V e circuitos para controle, que consomem um total máximo de potência estática de 850 A em 3.3 V de alimentação. O layout completo ocupa uma área de 300 x 700 m2 de silício. Os únicos componentes não integrados são 6x100 nF capacitores.

The demand for broadband wireless communication is growing rapidly, requiring more spectrum resources. However, spectrum usage is inefficient today because different frequency bands are allocated for different communication standards and most of the bands are not highly occupied. Cognitive radio systems with dynamic spectrum access improve spectrum efficiency, but they require wideband tunable receiver hardware. In such a system, a preselect filter is required for the RF receiver front end, because an out-of-band (OB) interferer can block the front end or cause distortion, desensitizing the receiver. In a conventional solution, off-chip passive filters, such as surface-acoustic-wave (SAW) filters, are used to reject the OB interferer. However, such passive filters are hardly tunable, have large area, and are very expensive. On-chip, high-selectivity, linearly tunable RF filters are, therefore, a hot topic in RF front-end research. Switched-capacitor (SC) RF filters, such as N-path filters, feature good linearity and tunability, making them good candidates for tunable RF filters. However, N-path filters have some drawbacks: notably, a poor harmonic response and limited close-by blocker tolerance. This thesis presents the design and implementation of several interferer-tolerant receivers based on SC technology. We present an RF receiver with a harmonic-rejecting N-path filter to improve the harmonic response of the N-path bandpass filter. It features tunable narrowband filtering and high attenuation of the third- and fifth-order LO harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2-1 GHz RF receiver is implemented in a 65 nm CMOS process. The blocker 1 dB compression point (B1dB) is -2.4 dBm at a 20 MHz offset, and remains high at the third- and fifth-order LO harmonics. The LNA’s reverse isolation helps keep the LO emission below -90 dBm. A two-stage harmonic-rejection approach offers a > 51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration. To improve tolerance for close-by blockers, we further present an SC RF receiver achieving high-order, tunable, highly linear RF filtering. We implement RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering and downconversion using only switches and capacitors in a 0.1-0.7 GHz prototype with tunable center frequency, programmable filter order, and very high tolerance for OB blockers. The 40 nm CMOS receiver consumes 38.5-76.5mA, achieves 40 dB gain, 24 dBm OB IIP3, 14.7 dBm B1dB for a 30MHz blocker offset, 6.8-9.7 dB noise figure, and > 66dB calibrated harmonic rejection ratio. The key drawback of our earlier SC receiver is the relatively high theoretical lower limit of the noise figure. To improve the noise performance, we developed a 0.1-0.6 GHz chopping SC RF receiver with an integrated blocker detector. We achieve RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping with passive SC circuits only. The 34-80 mW 65 nm receiver achieves 35 dB gain, 4.6-9 dB NF, 31 dBm OB-IIP3, and 15 dBm B1dB. The 0.2 mW integrated blocker detector detects large OB blockers with only a 1 us response time. The filter order can be adapted to blocker power with the blocker detector.

A qualidade da energia elétrica tem sido objeto constante de estudos, pois problemas inerentes a ela podem trazer grandes prejuízos econômicos, principalmente em processos industriais. Dentre os vários fatores que afetam a qualidade da energia elétrica, destacamos aqueles relacionados com os transitórios, originados pelo chaveamento de banco de capacitares nas redes elétricas de distribuição primária. Neste trabalho, além das características dos transitórios provenientes da energização de bancos de capacitares da concessionária, são analisados fatores que influenciam em suas intensidades. As condições sob as quais estes transitórios são atenuados foram investigadas. Além disto, é feita uma análise espectral das ondas de corrente e tensão, permitindo que sejam revelados os componentes harmônicos que podem afetar o funcionamento de equipamentos de controle, proteção e cargas sensíveis da indústria. Um circuito que representa um sistema real de distribuição, 13,8 kV, da concessionária CPFL (Cia Paulista de Força e Luz) foi simulado através do ATP (Alternative Transients Program). / The quality of electric power has been a constant topic of study, because inherent problems to it can bring great economic losses, mainly in industrial processes. Among the several factors that atfect power quality, those related to the transients originated by capacitar bank switching in the primary distribution systems must be highlighted. In this work, the characteristics of the transients resulting from the switching of the utility capacitor banks are analyzed, as well as factors that influence their intensities. The conditions under which these effects are mitigated was investigated. In addition, a spectral analysis of the current and voltage waves is made. This procedure can reveal the harmonic components that can affect the operation of control and protection equipment, as well as sensitive Ioads of the industry. A circuit that represents a real distribution system, 13.8 kV, from CPFL (Cia Paulista de Força e Luz) utility, was simulated through the software ATP (Alternative Transients Program).

<div>For over 20 years, biaxially oriented polypropylene (BOPP) has been used in capacitors as the dielectric material. BOPP has very high breakdown strength, low electric loss, and is relatively inexpensive however, it suffers from low dielectric constant and low usage temperature. The ever growing technology market requires more robust capacitors which can be used in high temperature and pulsed power applications, and the aim of this research is to meet or exceed dielectric properties of BOPP by combining specific polymer materials in layered structures, biaxially orienting the films, and heat setting the films to further improve thermal stability. Post-processing is done on custom built machines which track real-time true stress, true strain and birefringence values, allowing for a more complete picture of mechano-optical properties generated during the stretching process. These data, along with offline characterization techniques such as X-ray scattering and DSC, were coupled with dielectric property testing to help form relationships between polymer processing, morphology, and dielectric properties.</div><div><br></div><div>In Chapter 3, microlayer PET and PVDF (50:50 ratio) films with 32 total layers and thickness around 125 micron were provided by PolymerPlus. Films were first stretched uniaxially at varying temperatures in order to optimize processing conditions. Characterization confirmed PVDF crystal form transformation from alpha to beta form when films were stretched at 95^oC, and presence of - PVDF when stretched in molten state at 185^oC, sandwiched between solid PET layers. Dielectric properties were tested for films stretched at 150^oC, which exhibited low dielectric constant when PVDF spherulites or smaller, broken up fibrils were present, but improved dielectric constant when PVDF morphology consisted of long, highly ordered fibrils. Uniaxial drawing helped lower dielectric loss, and it further signicantly decreased at very high strains. In this case, morphology of uniaxially drawn PET did not have a strong correlation with dielectric constant, but higher PET crystallinity and orientation likely helps to lower dielectric losses.</div><div><br></div><div>Polymer microlayer fims consisting of 32 layers, 50:50 ratio PET to PVDF films were also studied extensively using thermal heat setting technique. Samples with good thickness uniformity after stretching were selected for these experiments, and offline characterization techniques were applied to study morphology. Films were annealed at temperatures around PVDF melting peak, which caused transformation of PVDF polymorphs from primarily alpha to combined gamma and/or gamma' forms. When oriented at 150^oC to 1.5X1, and ' -PVDF were detected in small amounts (via DSC) after annealing at 172^oC, and only ' after higher temperature annealing. Stretching at 150^oC to higher strains produced high amounts of '-PVDF only when annealed at 155^oC for films stretched to 3.5X1, and annealed at 150^oC for films stretched to 2.5X1. Offline characterization led to development of a structural model for PVDF layers alone, by de-laminating film layers. Then, morphology was correlated with dielectric properties by testing lms at room temperature, and at constant frequency, in temperature ramping experiments. Temperature ramping dielectric experiments showed that high percent crystallinity of PET may also help improve loss behavior at high temperatures. Furthermore, samples containing gamma and/or gamma'-PVDF had increasing dielectric constant with increasing temperature, however dielectric loss also greatly increased with increasing temperature. A significant conclusion was that the annealed sample without gamma or gamma'-PVDF present had only a slightly lower dielectric constant at high temperature testing, but also had much lower loss, making it a potential candidate for high temperature capacitor applications.</div><div><br></div><div>Other materials for potential dielectric film applications were studied as well. Two fluoropolymer films consisting of monolayers of ETFE and THV were uniaxially oriented and their morphology was characterized offline to elucidate structure-process-property relationships. Film samples produced were not large enough to be tested for dielectric properties, however morphology development during uniaxial orientation was evaluated. Both films showed nearly affine stretching behavior, and mechano-optical properties were studied during stretching at several temperatures. Combinations of X-ray scattering experiments and AFM led to proposed morphological structure models for each material at varying levels of deformation.</div><div><br></div><div>Finally, in collaboration with A. Schulman, Inc., PET and EVOH compounded blend and three layer PET-EVOH-PET films were oriented uniaxially and the morphology of the two was compared to each other. Potential applications include high barrier food packaging applications, due to the very high oxygen barrier but poor water vapor barrier of EVOH, which can be complimented by PET's high water vapor barrier. Uniaxial orientation of these two film systems showed that mechano-optical behavior was significantly different for blend versus layered films. Crystalline orientation factors were calculated from 1D WAXS data, which showed PET orientation was largely unaffected by increasing EVOH content in blend films, but blending decreased orientation of EVOH. PET's orientation in layered films was also largely unaffected by amount of EVOH in inner layer. EVOH's orientation factor was higher in all layered film compositions compared to neat EVOH film after stretching, suggesting that the coextrusion process is beneficial to increasing orientation of EVOH.</div><div><br></div>