abstract: Gallium-based liquid metals are of interest for a variety of applications including flexible electronics, soft robotics, and biomedical devices. Still, nano- to microscale device fabrication with these materials is challenging because of their strong adhesion to a majority of substrates. This unusual high adhesion is attributed to the formation of a thin oxide shell; however, its role in the adhesion process has not yet been established. In the first part of the thesis, we described a multiscale study aiming at understanding the fundamental mechanisms governing wetting and adhesion of gallium-based liquid metals. In particular, macroscale dynamic contact angle measurements were coupled with Scanning Electron Microscope (SEM) imaging to relate macroscopic drop adhesion to morphology of the liquid metal-surface interface. In addition, room temperature liquid-metal microfluidic devices are also attractive systems for hyperelastic strain sensing. Currently two types of liquid metal-based strain sensors exist for inplane measurements: single-microchannel resistive and two-microchannel capacitive devices. However, with a winding serpentine channel geometry, these sensors typically have a footprint of about a square centimeter, limiting the number of sensors that can be embedded into. In the second part of the thesis, firstly, simulations and an experimental setup consisting of two GaInSn filled tubes submerged within a dielectric liquid bath are used to quantify the effects of the cylindrical electrode geometry including diameter, spacing, and meniscus shape as well as dielectric constant of the insulating liquid and the presence of tubing on the overall system's capacitance. Furthermore, a procedure for fabricating the two-liquid capacitor within a single straight polydiemethylsiloxane channel is developed. Lastly, capacitance and response of this compact device to strain and operational issues arising from complex hydrodynamics near liquid-liquid and liquid-elastomer interfaces are described. / Dissertation/Thesis / Masters Thesis Materials Science and Engineering 2015

abstract: The greenhouse gases in the atmosphere have reached a highest level due to high number of vehicles. A Fuel Cell Hybrid Electric Vehicle (FCHEV) has zero greenhouse gas emissions compared to conventional ICE vehicles or Hybrid Electric Vehicles and hence is a better alternative. All Electric Vehicle (AEVs) have longer charging time which is unfavorable. A fully charged battery gives less range compared to a FCHEV with a full hydrogen tank. So FCHEV has an advantage of a quick fuel up and more mileage than AEVs. A Proton Electron Membrane Fuel Cell (PEMFC) is the commonly used kind of fuel cell vehicles but it possesses slow current dynamics and hence not suitable to be the sole power source in a vehicle. Therefore, improving the transient power capabilities of fuel cell to satisfy the road load demand is critical. This research studies integration of Ultra-Capacitor (UC) to FCHEV. The objective is to analyze the effect of integrating UCs on the transient response of FCHEV powertrain. UCs has higher power density which can overcome slow dynamics of fuel cell. A power management strategy utilizing peak power shaving strategy is implemented. The goal is to decrease power load on batteries and operate fuel cell stack in it’s most efficient region. Complete model to simulate the physical behavior of UC-Integrated FCHEV (UC-FCHEV) is developed using Matlab/SIMULINK. The fuel cell polarization curve is utilized to devise operating points of the fuel cell to maintain its operation at most efficient region. Results show reduction of hydrogen consumption in aggressive US06 drive cycle from 0.29 kg per drive cycle to 0.12 kg. The maximum charge/discharge battery current was reduced from 286 amperes to 110 amperes in US06 drive cycle. Results for the FUDS drive cycle show a reduction in fuel consumption from 0.18 kg to 0.05 kg in one drive cycle. This reduction in current increases the life of the battery since its protected from overcurrent. The SOC profile of the battery also shows that the battery is not discharged to its minimum threshold which increasing the health of the battery based on number of charge/discharge cycles. / Dissertation/Thesis / Masters Thesis Mechanical Engineering 2017

abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

L'évolution de la microélectronique est rythmée par l'augmentation constante du nombre de transistors intégrés dans chaque circuit grâce à la miniaturisation des dispositifs. Face à des coûts de fabrication et de développement de plus en plus élevés d'une part et à l'apparition de phénomènes parasites de plus en plus importants dans les dispositifs miniaturisés d'autre part, l'industrie se tourne progressivement vers l'intégration tridimensionnelle où les circuits sont empilés. La phase suivante de cette évolution pourra consister en la fabrication de circuits eux-mêmes tridimensionnels avec des composants répartis sur plusieurs niveaux. Dans ce contexte, la croissance catalysée de nanofils par CVD permet d'obtenir des structures cristallines en silicium sans relation d'épitaxie et de dimensions nanométriques sans photolithographie agressive. Nous avons utilisé ces propriétés pour la réalisation de démonstrateurs de capacités MOS et MIM ultra-denses de respectivement 22 µF/cm² et de 9 µF/cm² grâce à l'importante surface déployée par une assemblée de nanofils. Ces valeurs correspondent à des gains en surface appotée par les nanofils de 27,5 et de 16 pour les capacités MOS et MIM. Nous présentons dans ce travail de thèse, le dimensionnement, la fabrication et la caractérisation de ces dispositifs, depuis la croissance des nanofils jusqu'à l'obtention du démonstrateur complet. Nous nous sommes également intéressés aux principales briques technologiques de la fabrication de transistors verticaux à base de nanofils pour les niveaux d'interconnexion. Nous avons pour cela mis au point une technologie de croissance guidée de nanofils et étudié les qualités d'interface de l'empilement d'une grille déposé à basse température sur les nanofils. Cette étude s'appuie sur la comparaison des propriétés électriques de capacités MOS à base de nanofils obtenus par croissance catalysée avec les mêmes nanostructures obtenues par épitaxie sélective. Les nanofils catalysés présentent une très bonne qualité d'interface avec un empilement à base d'alumine et de nitrure de titane. Les technologies mises au point dans cette thèse ouvrent de nouvelles opportunités pour l'intégration tridimensionnelle au sein d'une même puce. / The main focus of microelectronic industry has been to increase the number of integrated transistors in each circuit thanks to the device miniaturization. However, due to the increasing manufacturing and development costs combined with the increase of parasitic phenomena in transistors when the dimensions decrease, the microelectronic industry is now focusing on the three-dimensional integration in which strategy, the circuits are stacked. The next step of this tendency will be able to consist in a component stacking inside the same three-dimensional circuit. In this context, the catalyzed CVD grown silicon nanowires are a very promising material since they can be grown with a crystalline structure without any epitaxial relationship. They can also have nanoscale dimensions without any aggressive photolithography step. We report in this thesis, the nanowire integration in high density MOS and MIM capacitors using the high developed surface of a nanowire assembly. This way, we have obtained capacitance densities of 22 µF/cm² and of 9 µF/cm² for MOS and MIM capacitors respectively. In this work, we present how the devices have been designed, fabricated and characterized from the nanowire growth to the complete devices. We have also studied the main steps of the nanowire integration MOS transistors for the interconnects. A guided nanowire growth process has been developed and the interface quality of a low temperature deposited gate stack has been investigated. This study is based on a comparison of MOS capacitor electrical performances between catalyzed and unanalyzed silicon nanowires obtained by selective epitaxial growth. The catalyzed nanowires show a very good interface quality with a gate stack composed of alumina and titanium nitride. The technologies developed in this thesis open new opportunities for the 3D integration of devices on the same chip.STAR

This work presents an energy system design for wireless sensor networks (WSNs) after applying our design the WSN should theoretically have an infinite lifetime. Energy harvesting sources can provide suitable energy for WSN nodes and reduce their dependence on battery. In this project, an efficient energy harvesting and storage system is proposed. By using (two supercapacitors and four DC/DC converters with step up /step down capabilities) all of them controlled by Microcontroller via switches to consider the best way to save energy to keep the WSN alive as long as possible. The usage of supercapacitors as an energy buffer to supply the sensor components (microcontroller and radio) with energy it needs to work. We could control the energy flow according to a specific voltage levels in supercapacitors to guaranty the full functionality for WSN with minimizing the loss of energy, and that’s leads to long time life for the wireless sensor node WSN. Another important thing we find in our experiment that is the inner leakage of the supercapacitor and how it has a critical effect on how long it can serve our system with energy. This paper contains on two theoretical sections (Part one and part two) which are based on literature reviews, and one experimental section (Part three) based on experimental building the prototype, coding and testing.

Made available in DSpace on 2014-06-11T19:22:33Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-08-29Bitstream added on 2014-06-13T20:09:45Z : No. of bitstreams: 1 pereirajunior_br_me_ilha.pdf: 2079589 bytes, checksum: 086f2d874ba748765509a09a3555c74f (MD5) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Manter o perfil de tensão da rede de distribuição dentro dos limites operacionais adequados é um problema que deve ser modelado e resolvido obedecendo às restrições de natureza técnica e econômica. Após um período de construção da rede de distribuição ocorre degradação da qualidade do perfil de tensão como conseqüência das dificuldades de prever condições precisas durante a fase de planejamento do sistema. Desta maneira torna-se necessário o planejamento de curto prazo da rede de distribuição como a instalação de dispositivos que assegurem que o sistema opere dentro dos limites de magnitude de tensão estabelecidos pelas agências reguladoras. Dentre os dispositivos, destaca-se a alocação de bancos de capacitores, que instalados de forma adequada proporcionam a compensação de reativos, regulando as magnitudes das tensões ao longo da rede bem como o fator de potencia da subestação e fornecendo como benefício secundário a redução de perdas ativas no sistema. O problema de alocação de bancos de capacitores em sistemas de distribuição de energia elétrica consiste em determinar os tipos, capacidade, localização e esquemas de controle dos bancos alocados. Neste trabalho apresenta-se uma nova metodologia para alocar bancos de capacitores fixos e chaveados em alimentadores de distribuição. Esta metodologia contempla as necessidades de representar o comportamento estocástico dos diferentes tipos de cargas conectadas ao sistema de distribuição e a característica topológica das redes de distribuição que não apresentam mais estrutura radial, devido à presença de geradores distribuídos ligados diretamente à rede. O problema de alocação de bancos de capacitores fixos e chaveados é formulado como um modelo de programação não linear inteiro misto multiobjetivo e para solução deste modelo é proposto um algoritmo genético multiobjetivo e uma algoritmo busca tabu multiobjetivo / Maintaining the voltage profile of distribution networks within the operational limits is a problem that must be modeled and solved according to economical and technical restrictions. Afterwards a period of constructing the distribution network, there is degradation of the quality of the voltage profile as a consequence of the difficulties in predicting precise conditions during the planning phase. This way, it is necessary the short term distribution planning and the installation of devices that assure the system operating within the voltage magnitudes fixed by the regulating agencies. Among the devices, there are allocation of capacitor banks, that when adequately installed provide the reactive compensation, regulating the voltage magnitude along the network as well as the substation power factor and providing as a secondary result reducing the active losses of the system. The problem of allocating capacitor banks in electrical energy distribution systems consists in determining the types, capacity, localization and control techniques of the allocated Banks. This work presents a new methodology for allocating fixed and switched capacitor banks in distribution feeders. This methodology attends the needs of representing the stochastic behavior of the different types of the loads connected to the distribution system and the topological characteristics of the distribution networks that do not present radial structure, due to the distributed generators connected directly to the network. The problem of allocating fixed and switched capacitor banks is formulated as a mixed multi objective nonlinear integer programming model and for solution of this model is proposed a multi objective genetic algorithm and a multi objective tabu search algorithm

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Circuits for sampling and retention of analogue signals are commonly implemented with techniques such as switched capacitors (SC). SC circuits employing the storage of charge in a linear capacitor to represent a signal in the form of voltage. Operational Amplifiers (AmpOp's) are used to transfer the load of a capacitor to another, sampling and holding circuits for analogue signals in closed loop. Recently, another technique has been developed without the need of building linear capacitors, making possible projects compatible with VLSI CMOS processes. This technique, called Switched Current (SI), is characterized by processing the signals in the current form, and implemented through the memory retention of electric charge on the gate of a MOS transistor in saturation zone. The charge is hold in a gate-source voltage and hence the current in a transistor. In this model, the excursion of the signal is not directly dependent on the supply voltage, but dependent on the polarization and current signal. This makes the model attractive for low voltage. The technique does not require AmpOp's and capacitors. The speed of the circuit is not limited by AmpOp's and its gainbandwidth product, but by design and manufacturing process. This technique is not yet consolidated and its performance is still not competitive with SC circuits [1] However, SI circuits become interesting as they constitute an open field for future research and the opportunity to be fully implemented in processes manufacturing oriented to purely digital circuits. This work begins with a framework of the subject matter, placing the reader in the state of the art manufacturing technology and some implications that directly affect analog circuits. Are also presented in this section some implementations which serve to characterize what is being done recently in terms of Sigma Delta (ΣΔ) modulators. Abstract vi In Chapter 2, are made a review of sampling and holding bases, the AD conversion techniques with focuses in oversampled AD converters, the circuits that implementing SC and SI modulators and their influences, and finally a review of the nonidealities that involve the practice of project. Chapter 3 a comparative study is done between memory cells SC and SI. Based on a simplified model of small signals, the behavior analyzes on the signal-noise-ratio (SNR), power consumption and speed, providing indications of performance throughout the operating region of MOS transistors. Chapter 4 deals with the initial specifications for the development of a ΣΔ AD converter for a specific implementation. The s tudies and estimates lead to pre-design of the project's ultimate goal the creation of a ΣΔ modulator in the SC and SI techniques. In Chapter 5 is intended to make the measures and tests that establish the standards of comparison, the discussion of results and conclusions. Finally, in Chapter 6, an alternative proposal is presented based on an architecture that performs a sigma-delta modulator with low distortion, implemented with SI circuit. The final conclusions and contributions are presented in Chapter 7. / Circuitos de amostragem e retenção de sinais analógicos são comumente implementados com técnicas de chaveamento de capacitores (Switched Capacitor SC). Circuitos SC empregam o armazenamento de cargas em um capacitor linear para representar um sinal sob a forma de tensão. Amplificadores Operacionais (AmpOp s) são usados para transferir essa carga de um capacitor a outro, amostrando e retendo sinais analógicos em circuitos de malha fechada. Recentemente, uma outra técnica tem sido desenvolvida sem a necessidade de construção de capacitores lineares, tornando possíveis projetos compatíveis com processos de fabricação VLSI CMOS. Esta técnica, chamada de Switched Current (SI), caracteriza-se por processar os sinais sob a forma de correntes, sendo a operação de memorização implementada através da retenção de carga elétrica na porta de um transistor MOS na zona de saturação. A carga retida corresponde a uma tensão portafonte e, conseqüentemente, a uma corrente no transistor. Neste modelo, a excursão do sinal não é diretamente dependente da tensão de alimentação, mas dependente das correntes de polarização e de sinal. Isso torna o modelo atrativo para baixas tensões. A técnica não requer AmpOp s e implementação física de capacitores. A velocidade do circuito não é limitada por AmpOp s e seu produto ganho-banda, mas pelo projeto e processo de fabricação. Essa técnica ainda não está consolidada e sua performance ainda não é competitiva com os circuitos SC [1], Contudo, os circuitos SI tornam-se interessantes na medida em que constituem um campo aberto para futuras pesquisas e pela possibilidade de serem completamente implementados em processos de fabricação voltados a circuitos puramente digitais. Este trabalho inicia com um enquadramento do trabalho proposto, situando o leitor no contexto do estado da arte das tecnologias de fabricação e algumas implicações diretas que afetam circuitos analógicos. São apresentadas ainda nesta seção algumas implementações que servem para caracterizar o que está sendo feito recentemente em termos de conversores tipo Sigma Delta (ΣΔ). No Capítulo 2, faz-se o embasamento sobre as técnicas utilizadas no processo de amostragem e retenção utilizadas para conversão ADΣΔ e uma revisão das não idealidades que envolvem a prática de projeto. No Capítulo 3 é feito um estudo comparativo, entre células de memória SC e SI. Baseado em modelo simplificado de pequenos sinais, analisa-se o comportamento quanto à relação-sinal-ruido (SNR), ao consumo e à velocidade, fornecendo indicações de desempenho em toda região de funcionamento dos transistores MOS. No Capitulo 4 são abordadas as especificações iniciais ao desenvolvimento de um conversor ΣΔ para uma implementação específica. Os estudos e estimativas que conduzem a pré-concepção do projeto têm como objetivo final a geração de um modulador ΣΔ nas técnicas SC e SI. Nos Capítulos 5 efetuam-se as medidas e testes que estabelecem os padrões de comparação, a discussão dos resultados e conclusões. Por fim, no Capítulo 6, uma proposta alternativa é apresentada com base em uma arquitetura de modulador sigma-delta de baixa distorção, implementada em circuito SI. As conclusões e contribuições finais são apresentadas no capítulo 7.

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2016-02-03T20:53:53Z No. of bitstreams: 1 AlanPauloOliveiraDaSilva_TESE.pdf: 1827762 bytes, checksum: f478a28631ce88521aefb0bb1971ecff (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2016-02-04T00:09:56Z (GMT) No. of bitstreams: 1 AlanPauloOliveiraDaSilva_TESE.pdf: 1827762 bytes, checksum: f478a28631ce88521aefb0bb1971ecff (MD5) / Made available in DSpace on 2016-02-04T00:09:56Z (GMT). No. of bitstreams: 1 AlanPauloOliveiraDaSilva_TESE.pdf: 1827762 bytes, checksum: f478a28631ce88521aefb0bb1971ecff (MD5) Previous issue date: 2015-01-30 / Este trabalho prop?e a utiliza??o do modelo comportamental do ciclo de histerese do capacitor ferroel?trico como uma nova alternativa ?s t?cnicas normalmente custosas no c?lculo de fun??es n?o-lineares em neur?nios artificiais implementados em plataforma de hardware reconfigur?vel, no caso, um dispositivo FPGA. Inicialmente a proposta foi validada por meio da implementa??o da l?gica booleana atrav?s dos modelos digitais de dois neur?nios artificiais: o Perceptron e uma varia??o do modelo Spiking Neuron Integrate and Fire, ambos utilizando o modelo tamb?m digital do ciclo de histerese do capacitor ferroel?trico como unidade b?sica n?o-linear no c?lculo das sa?das dos neur?nios. Finalmente, foi utilizado um modelo anal?gico do capacitor ferroel?trico com o objetivo de verificar a sua efic?cia e uma poss?vel redu??o no n?mero de elementos l?gicos necess?- rios no caso da implementa??o dos neur?nios em circuito integrado. As implementa??es foram realizadas por meio de modelos em Simulink e a sintetiza??o dos mesmos foi feita com o aux?lio do software DSP Builder, da Altera Corporation. / This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it?s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it?s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2016-08-16T20:12:23Z No. of bitstreams: 1 EdsonSilvaDoNascimento_DISSERT.pdf: 2737774 bytes, checksum: 77ef6f8833e63d26e699ee6f42209b93 (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2016-08-17T21:43:01Z (GMT) No. of bitstreams: 1 EdsonSilvaDoNascimento_DISSERT.pdf: 2737774 bytes, checksum: 77ef6f8833e63d26e699ee6f42209b93 (MD5) / Made available in DSpace on 2016-08-17T21:43:01Z (GMT). No. of bitstreams: 1 EdsonSilvaDoNascimento_DISSERT.pdf: 2737774 bytes, checksum: 77ef6f8833e63d26e699ee6f42209b93 (MD5) Previous issue date: 2016-04-08 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior (CAPES) / Este trabalho tem como objetivo encontrar um material alternativo para os atuais capacitores de t?ntalo usados na ind?stria. O ni?bio ? um substituto em potencial por ser mais leve e barato que o t?ntalo. Eles pertencem ao mesmo grupo da tabela peri?dica e, desta forma, apresentam v?rias propriedades f?sicas e qu?micas semelhantes. O ni?bio ? usado em diversas aplica??es tecnologicamente importantes, e o Brasil possui as maiores reservas mundiais, em torno de 96%. Esses capacitores eletrol?ticos possuem alta capacit?ncia especifica, ou seja, podem armazenar altas energias em volumes pequenos comparados a outros tipos de capacitores. A rota de produ??o do capacitor de ni?bio foi realizada atrav?s das etapas de processamento da metalurgia do p?. Inicialmente, o p? de ni?bio foi caracterizado atrav?s de DRX, MEV, granulometria a laser; e depois peneirado para apresentar uma granulometria de 400mesh. Posteriormente o p? foi compactado com uma matriz especial e ent?o sinterizado em diferentes temperaturas e tempos de isoterma. Ap?s a sinteriza??o as amostras passaram por processo de oxida??o an?dica em diferentes tens?es para a obten??o de uma camada ?xida, a qual desempenha o papel do diel?trico do capacitor. Os resultados foram obtidos atrav?s de uma ponte de capacit?ncia, mostrando a forte influ?ncia da sinteriza??o e do processo de oxida??o an?dica na produ??o dos capacitores. Os melhores resultados foram obtidos para o p? sinterizado a 1400?C durante 60 minutos e anodizados a uma tens?o de 10V. O processo apresentou valores significativos e com mais estudos pode-se melhorar ainda mais esses valores para competirem com o t?ntalo. / It seeks to find an alternative to the current tantalum electrolytic capacitors in the market due to its high cost. Niobium is a potential replacement for be lighter and cheaper than tantalum. They belong to the same table group periodically and thus exhibit several physical and chemical properties similar. Niobium is used in many technologically important applications, and Brazil has the largest reserves, around 96%. These electrolytic capacitors have high specific capacitance, so they can store high energy in small volumes compared to other types of capacitors. This is the main attraction of this type of capacitor because is growing demand in the production of capacitors with capacitance specifies increasingly high, this because of the miniaturization of various devices such as GPS devices, televisions, computers, phones and many others. The production route of the capacitor was made by powder metallurgy. The initial niobium poder was first characterized by XRD, SEM and laser particle size to then be sieved into particle size 400mesh. The powder was then compacted at pressure of 150MPa and sintered at 1400, 1450 and 1500?C using two sintering time 30 and 60min. Sintering is an important part of the process as it affects properties as porosity and surface cleaning of the samples, which greatly affected the quality of the capacitor. After sintering the samples were underwent a process of anodic oxidation (anodizing), which created a thin film of niobium pentoxide over the whole surface of the sample, this film is the dielectric capacitor. The anodizing process variables influenced a lot in film formation and consequently the capacitor. The samples were characterized by electrical measurements of capacitance, loss factor and ESR (equivalent series resistance). The sintering has affected the porosity and in turn the specific area of the samples. The capacitor area is directly related to the capacitance, that is, the higher the specific area is the capacitance. Higher sintering temperatures decrease the surface area but eliminate as many impurities. The best results were obtained at a temperature of 1400?C with 60 minutes. The most interesting results were compared with the specific capacitance and ESR for all samples.

Este trabalho apresenta um conversor CC - CC baseado em Capacitores Chaveados de 6 fases e tempos intercalados com o objetivo de coletar energia fotovoltaica projetado em tecnologia CMOS de 130 nm para ser usado em aplicações em Internet das Coisas e Nós Sensores. Ele rastreia o máximo ponto de entrega de energia de um painel fotovoltaico policristalino de 3 cm x 3 cm através de modulação da frequência de chaveamento com o objetivo de carregar baterias. A razão da tensão de circuito aberto foi a estratégia de rastreio escolhida. O conversor foi projetado em uma tecnologia CMOS de 130 nm e alcança uma eficiência de 90 % para potencias de entrada maiores do que 30 mW e pode operar com tensões que vão de 1.25 até 1.8 V, resultando em saídas que vão de 2.5 até 3.6, respectivamente. Os circuitos periféricos também incluem uma proteção contra sobre tensão na saída de 3.6 V e circuitos para controle, que consomem um total máximo de potência estática de 850 A em 3.3 V de alimentação. O layout completo ocupa uma área de 300 x 700 m2 de silício. Os únicos componentes não integrados são 6x100 nF capacitores.