Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

<p>        The last decade has witnessed an explosive growth in highly data-centric applications such as Internet of Things (IoT) and Artificial Intelligence (AI). Such applications demand highly efficient data storage and processing, especially when the systems operate under high energy/resource constraints, such as in intermittent-powered systems or edge AI platforms. Therefore, at the hardware level, high storage capacity along with low power operations has become more crucial than ever. Although conventional silicon-based complementary metal-oxide semiconductor (CMOS) has brought great prosperity to the semiconductor industry to date, enabling high-performance computing, increasing leakage energy and low cell density hinder their ability to sustain their benefits at scaled nodes and meet the demands of emerging data-intensive workloads. On the other hand, emerging non-volatile memories (NVMs) have gained much attention due to their distinct advantages over CMOS, such as zero leakage, high density, and non-volatility. However, they suffer from issues associated with high write power, endurance and/or variability. Thus, there is a need for new memory technologies that offer high density, low power and high-performance attributes to meet the data storage and efficiency demands of the new workloads. Furthermore, such technological advances need to be supported by architectural innovations. Despite hardware advances, the energy efficiency gains in traditional von-Neumann architectures are limited by power-hungry data movements between memory and processor, also known as the memory bottleneck. To alleviate this issue, in-memory computing (IMC) has emerged as a promising technique, wherein certain computations are executed within a memory macro, thus reducing processor-memory transactions. Along similar lines, incorporating non-volatile storage in logic state elements, such as flip-flops, has gained much attention for intermittently-powered systems, wherein the state of the processor is efficiently backed-up in the local non-volatile memory in the event of a power failure. Such techniques enabling logic-memory synergy reduce compute, storage, and/or communication costs and thus can be highly promising for future computing platforms. However, existing techniques for logic-memory fusion suffer from key design bottlenecks that need to be mitigated via extensive technology-circuit-architecture co-design. In this dissertation, we address some of the issues associated with data storage and processing by exploring spin-based low-power non-volatile devices, their memory applications, and logic-memory coupling enabled by their unique technological attributes. </p> <p>      We propose spin-based devices that employ the valley-spin Hall (VSH) effect in monolayer transition metal dichalcogenides (TMDs), such as tungsten di-selenide (WSe2). With the unique features of WSe2, the proposed devices are designed to have an integrated back-gate, enabling control of the charge and spin currents in 2D TMD channel. This design leads to an access-transistor-less compact layout in memory arrays. The generated spin currents diverge into opposite directions with out-of-plane spins, allowing for the coupling of WSe2 with perpendicular magnetic anisotropy (PMA) magnets. This enables low-power write operations and facilitates differential logic encoding within a single device. Additionally, we utilize inter-layer exchange-coupling mediated by FeCo-oxide and Ta layers to electrically isolate but magnetically couple the PMA free layers. This configuration benefits read performance by achieving low series resistance in the read path. To ensure reliable inter-layer coupling and the functionality of the proposed devices, we perform micromagnetic OOMMF simulations and extensively investigate the impact of process variations on the exchange-coupled PMA free layers. From the simulations, we conclude that the proposed design is resilient to potential process variations arising from misalignment of the PMA free layers and reductions in exchange-coupling strength. Based on the proposed devices, we explore circuit designs for logic and memory applications. </p> <p>      First, we propose VSH effect-based non-volatile flip-flops (VSH-NVFFs) using the proposed devices to introduce non-volatility in logic targeted for intermittently powered systems. The key challenge to design such systems is to enable energy-efficient data back-up in the event of power failure. In our design, we achieve high energy-efficiency via device-circuit co-design of VSH devices and NVFFs. We propose two flavors of NVFFs: NVFF-1 with a compact design and NVFF-2 targeted for lowering data restore energy. Compared to existing giant spin Hall (GSH) effect-based NVFFs, also known as spin-orbit torque or SOT-NVFFs, our NVFFs exhibit 68%-71%, 74%-75% and 55%-59% lower normal, back-up, and restore energies, respectively. Among the proposed VSH-NVFFs, NVFF-1 exhibits 8% lower operation energy than NVFF-2, while NVFF-2 exhibits 6% lower back-up energy and 11% lower restore energy. This result suggests that NVFF-1 is more suitable for systems with a smaller number of checkpointing operations (data back-up/restore), while NVFF-2 is beneficial for systems needing a larger number of checkpointing operations. Furthermore, by conducting Monte Carlo simulations, we confirm the reliable restore operation of the proposed NVFFs.</p> <p>      Secondly, we design memory arrays using the proposed devices to gain benefits over previously proposed VSH effect-based memory designs, in which read currents flow through a highly resistive 2D TMD channel, degrading read performance. For read operations, our memory array requires a read access transistor. By sharing the read access transistor per word, we minimize the area overhead in our memory array design. The area of our bit-cell is comparable to a previously proposed VSH memory, despite the inclusion of an additional read access transistor. Additionally, with the electrical isolation of the read and write paths in our design, we achieve improvements in read performance, with reductions of 39%-42% and 36%-46% in read time and energy, respectively. However, this improvement comes at the cost of write performance, with a 1.7X and 2.0X increase in write time and energy, respectively. We also achieve a 1.1X-1.3X larger sense margin (SM) and a 1.2X-1.3X improvement in read disturb margin (RDM). Furthermore, by increasing the size of the read access transistor in our memory array, we can further improve the SM by up to 1.5X-1.6X with only a 7%-12% area increase. Our design can be particularly useful for applications that involve frequent reads and few writes, such as neural accelerators.</p> <p>      We further expand our exploration of VSH effect-based devices for implementing IMC. As XNOR-based binary neural networks (BNNs) have shown immense promise for resource-intensive AI edge systems, their implementation has been explored using SRAMs and emerging NVMs. However, these designs typically need two bit-cells (2T-2R) to encode signed weights, resulting in an area overhead. Therefore, we address this issue by proposing a compact and low-power IMC technique for XNOR-based dot products. Our approach utilizes the VSH effect in monolayer WSe2 to design XNOR bit-cells that feature an access-transistor-less compact layout and differential weight encoding in a single device (XNOR-VSH). We co-optimize the proposed VSH device and the memory arrays to enable efficient in-memory dot product computations between signed binary inputs and signed binary weights. The compactness of the proposed XNOR-VSH array leads to 4.8%-9.0% lower compute latency and 36.6%-62.5% lower compute energy, along with 49.3%-64.4% smaller area compared to spin-transfer torque magnetic RAM (STT-MRAM) and SOT-MRAM based XNOR-arrays.</p> <p>      Lastly, we explore the modeling and design of voltage-controlled spintronic devices, which have shown remarkable potential for ultra-low-power and high-speed operation empowered by magnetoelectric (ME) materials. The proposed ME device utilizes a monolayer WSe2 channel placed on top of a Cr2O3 ME dielectric, which are electrostatically controlled by top and bottom gates. To capture the electrostatics in 2D TMD and the gate-voltage-dependent ME effect, we establish a modeling framework using a distributed capacitive network. This framework self-consistently accounts for the interactions between the various components. We verify the functionality of the proposed model by simulating the proposed device, and show how it can capture the device characteristics.</p>

This thesis presents work performed on explosively driven magnetic flux compression generators. This kind of devices converts the chemically stored energy in a high explosive into electromagnetic energy in the form of a powerful current pulse. The high energy density of the high explosives makes flux compression generators attractive as compact power sources. In order to study these devices a generator was designed at FOI in the mid-90ies. Two generators remained unused and became available for this licentiate work. The thesis reports experiments with, and simulations of, the operation of the two remaining generators. The aim was to fully understand the performance of the generator design and be able to accurately simulate its behaviour. The generators were improved and fitted with various types of diagnostics to monitor the generator operation. Two experiments were performed of which the first generator was operated well below its current capability limits while the second was stressed far above its limits. Since the generator generates a rapidly increasing current, a current measurement is the most important diagnostic revealing the current amplification of the generator and its overall performance. Further it is important to measure the timing of various events in the generator. With a common time reference it is possible to combine data from different probes and extract interesting information which cannot be directly obtained with a single measurement. Two types of numerical simulations have been performed: Hydrodynamic simulations of the high explosive interaction with the armature were used to verify the measured armature dynamics. A zero-dimensional code was used to perform circuit simulations of the generator. The model takes into account the inductance reduction due to the compression of the generator as well as the change in conductivity due to heating of the conductors in the generators. / QC 20101103

Die Anwenung von Operator-Splitting-Methoden auf gewöhnliche Differentialgleichungen ist gut etabliert. Für Differential-algebraische Gleichungen und partielle Differential-algebraische Gleichungen unterliegt sie jedoch vielen Einschränkungen aufgrund des Vorhandenseins von Nebenbedingungen. Die räumliche Diskretisierung reduziert PDAEs und lenkt unseren Fokus auf das Konzept der DAEs. Um eine reibungslose Übertragung des Operator-Splittings von ODEs auf DAEs durchzuführen, ist es wichtig, eine geeignete entkoppelte Struktur für das gewünschte Differential-algebraische System zu haben. In dieser Arbeit betrachten wir ein Modell, das partielle Differentialgleichungen für elektromagnetische Bauelemente - modelliert durch die Maxwell-Gleichungen - mit Differential-algebraischen Gleichungen koppelt, die die elementaren Schaltungselemente beschreiben. Nach der räumlichen Diskretisierung der klassischen Formulierung der Maxwell-Gleichungen mit Hilfe der finiten Integrationstechnik formulieren wir das resultierende gekoppelte System als Differential-algebraische Gleichung. Um eine geeignete Entkopplung zu bekommen, verwenden wir den zweigorientierten Loop-Cutset-Ansatz für die Schaltungsmodellierung. Daraus folgt, dass wir in der Lage sind, eine geeignete Operatorzerlegung so zu konstruieren, dass wir eine natürliche topologisch entkoppelte Port-Hamiltonsche DAE-Struktur erhalten. Wir schlagen einen Operator-Splitting-Ansatz für die Schaltungs-DAEs und gekoppelten Feld-Schaltungs-DAEs in entkoppelter Form vor und analysieren seine numerischen Eigenschaften. Darüber hinaus nutzen wir das Hamiltonsche Verhalten der inhärenten gewöhnlichen Differentialgleichung durch die Verwendung expliziter und energieerhaltender Zeitintegrations-methoden. Schließlich führen wir numerische Tests, um das mathematische Modell zu illustrieren und die Konvergenzergebnisse für das vorgeschlagene DAE-Operator-Splitting zu demonstrieren. / Le equazioni algebriche differenziali e algebriche alle derivate parziali hanno avuto un enorme successo come modelli di sistemi dinamici vincolati. Nella modellazione matem- atica, spesso si desidera catturare diversi aspetti di una situazione come le leggi di conservazione della fisica, il trasporto convettivo o la diffusione. Queste aspetti si riflettono nel sistema di equazioni del modello come operatori diversi. La tecnica dell’Operator Splitting si è rivelata una strategia di successo per affrontare problemi così complicati. L’applicazione dei metodi di Operator Splitting alle equazioni differenziali ordinarie (ODE) è ormai una tecnologia ben consolidata. Tuttavia, per equazioni algebriche differenziali (DAE) e algebriche differenziali parziali (PDAE), l’approccio è soggetto a molte restrizioni dovute alla presenza di vincoli e alla proprietà di indice. La discretizzazione spaziale riduce le PDAE e indirizza la nostra attenzione al concetto di DAE. Le DAE emergono in problemi dinamici vincolati come circuiti elettrici o reti di trasporto di energia. Al fine di generalizzare agevolmente la tecnica dell’Operator Splitting dalle ODE alle DAE, è importante avere una struttura disaccoppiata adeguata per il sistema algebrico differenziale desiderato. In questa tesi, consideriamo un modello che accoppia equazioni differenziali alle derivate parziali per dispositivi elettromagnetici -modellati dalle equazioni di Maxwell- con equazioni algebriche differenziali che descrivono gli elementi base del circuito. Dopo aver discretizzato spazialmente la formulazione classica delle equazioni di Maxwell usando la tecnica di integrazione finita, formuliamo il sistema accoppiato risultante come una equazione algebrica differenziale. Interpretando il dispositivo elettromagnetico come un elemento capacitivo, l’indice dell’intero sistema di circuito e campo accoppiato può essere specificato utilizzando le proprietà topologiche del circuito e non supera il valore di due. Per eseguire un disaccoppiamento appropriato, utilizziamo l’approccio loop-cutset per la modellazione dei circuiti. In tal modo siamo in grado di costruire una opportuna decomposizione dell’operatore tale da ottenere una naturale struttura disaccoppiata port-Hamiltonian DAE. Proponiamo un approccio di suddivisione dell’operatore per i DAE a circuito disaccoppiato e a circuito di campo accoppiato utilizzando gli algoritmi di divisione Lie-Trotter e Strang e per analizzare le proprietà numeriche di questi sistemi. Inoltre, sfruttiamo il comportamento hamiltoniano del sistema di equazioni differenziali ordinarie mediante l’utilizzo di metodi di integrazione temporale con esatta conservazione dell’energia. Poggiando sull’analisi di convergenza del metodo di suddivisione dell’operatore ODE, deriviamo i risultati di convergenza per l’approccio proposto che dipendono dall’indice delsistema e quindi dalla sua struttura topologica. Infine, eseguiamo prove numeriche di sistemi circuitali, nonchè sistemi accoppiati a circuito di campo, per testare il modello matematico e dimostrare i risultati di convergenza per la proposta Operator Splitting DAE. / The application of operator splitting methods to ordinary differential equations (ODEs) is well established. However, for differential-algebraic equations (DAEs) and partial differential-algebraic equations (PDAEs), it is subjected to many restrictions due to the presence of constraints. In constrained dynamical problems as electrical circuits or energy transport networks, DAEs arise. In order to perform a smooth transfer of the operator splitting from ODEs to DAEs, it is important to have a suitable decoupled structure for the desired differential-algebraic system. In this thesis, we consider a model which couples partial differential equations for electro- magnetic devices -modeled by Maxwell’s equations- with differential-algebraic equations describing the basic circuit elements. After spatially discretizing the classical formulation of Maxwell’s equations using the finite integration technique, we formulate the resulting coupled system as a differential-algebraic equation. To perform an appropriate decoupling, we use the branch oriented loop-cutset approach for circuit modeling. It follows that we are able to construct a suitable operator decomposition such that we obtain a natural topologically decoupled port-Hamiltonian DAE structure. We propose an operator splitting approach for the decoupled circuit and coupled field- circuit DAEs using the Lie-Trotter and Strang splitting algorithms and analyze its numerical properties. Furthermore, we exploit the Hamiltonian behavior of the system’s inherent ordinary differential equation by the utilization of explicit and energy-preserving time integration methods. Based on the convergence analysis of the ODE operator splitting method, we derive convergence results for the proposed approach that depends on the index of the system and thus on its topological structure. Finally, we perform numerical tests, to underline the mathematical model and to demonstrate the convergence results for the proposed DAE operator splitting.