<p dir="ltr"> Conventional RF switching technologies struggle to simultaneously achieve high-power handling, low loss, high isolation, broadband operation, quick reconfiguration, high linearity, and low cost, which are desirable for many applications, including communications, radar, and sensors. Moreover, they require electrical bias networks, which degrade performance and, in many cases, inhibit wideband applications, including DC operation. On the other hand, plasma (photoconductive) switches use an optical bias to generate free charge carriers. Recently these switches have begun to not only rival conventional technologies in terms of performance metrics such as switching speeds and loss but have exceeded what is possible in terms of power handling. This work details the strides made in placing solid-state plasma technologies at the forefront of advanced, high-power switching applications including a novel high-power tuner and an absorptive/reflective SPnT switch. In various form factors, SSP has achieved analog control of loss as low as 0.09 dB and isolation as high as 54 dB, linearity of 68.8 dBm (IP3), 110 GHz instantaneous bandwidth, including DC, switching speeds as low as 3.5 us, 100+ W power handling, and 30+ W hot switching. In addition, comprehensive physics modeling has been developed to enable seamless design validation before fabrication commences. This thesis discusses the achievements and design considerations for creating optimized plasma switches and proposes a path for future applications.</p>

<p>Most work on amplifier linearity has focused on the transconductance (gm) linearity, but there is increasing evidence that the voltage-dependence of the gate-source capacitance (Cgs) plays an important role in the linearity of emerging devices. This work addresses the capacitance contribution by incorporating the nonlinearities attributed to the voltage dependency of Cgs of a general FET on a circuit-level Cg amplifier model.</p> <p>An amplifier model including a voltage-dependent Cgs, and a voltage-dependent gm is studied using harmonic analysis and Volterra series. A closed form expression for the  third-order intercept point (IP3) of the amplifier, which depends on the nonlinear coefficients of Cgs, is obtained. A simple design rule, and a formula for the reduction of the IP3 due to the voltage-dependent Cgs are also presented. </p> <p>As application examples, the linearity of an amplifier based on a specific device is analyzed for two cases by extracting the nonlinear circuit parameters of the device. First for an analytic model of a bulk mosfet. Second for a one-dimensional, ballistic, coaxially gated Si nanowire. For low frequencies of design, the distortion introduced by gm is predominant, but for high frequencies it is obscured by the distortion coming from Cgs.</p> <p>We conclude that taking into account the voltage-dependence of Cgs is crucial when predicting the linearity behavior of a Cg amplifier, either designed for high-frequency operation, or based on a device operating near the quantum capacitance limit. </p>

<p dir="ltr">Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a hardware mechanism that makes microcontrollers forgo branch predictors, thereby removing branch mispredictions. The scope of this work is limited to low cost microcontroller cores that are applied in embedded systems. The proposed technique is implemented as five different modules which work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles except in cases where control transfer instructions are in true dependence with their immediate previous instructions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The critical path latency of instruction fetch stage integrated with the proposed architecture is 307 ps excluding the instruction cache access time.</p>

<p dir="ltr">In the ever-advancing landscape of technology, emerging technologies have emerged as<br>powerful catalysts for innovation across various domains. These technologies, situated at<br>the nexus of the physical and digital realms, hold tremendous potential for revolutionizing<br>industries, improving our quality of life, and addressing global challenges. Central to har-<br>nessing this potential is the efficient exchange of data and the processing of information, a<br>pivotal linchpin that underpins the success of emerging technologies.</p><p dir="ltr"><br>The thesis titled ”Empowering Emerging Technologies through Energy-Efficient Commu-<br>nication and In-Sensor Computing” delves into a critical facet of this technological revolution.<br>It explores the central role of energy-efficient communication and in-sensor computing in un-<br>locking the full potential of emerging technologies. This comprehensive exploration unfolds<br>across three distinct chapters, each addressing an essential aspect of the research undertaken.<br>The first two chapters are dedicated to the realm of wearable technology, where we delve<br>into the intricacies of Human Body Communication (HBC). Chapter 2 meticulously models<br>the human body, focusing on Galvanic excitation and termination, which are fundamental<br>to understanding communication within this unique domain. In Chapter 3, we introduce<br>a novel method employing resonance through the human body to enhance wearable device<br>functionality and efficiency, shedding light on its innovative potential.</p><p dir="ltr"><br>The fourth chapter takes us into the world of machine vision and computer vision, where<br>we unveil an ingenious solution—an ADC-less in-sensor image edge detection scheme. This<br>pioneering approach not only advances the field but also enables enhanced image processing<br>and analysis within sensors, thereby fostering the growth of machine vision applications.<br>This thesis represents a substantial contribution to the fields of HBC and in-sensor com-<br>puting. It models the Galvanic body channel, explores resonance-based power delivery and<br>communication, and demonstrates the importance of in-sensor image edge detection. Fur-<br>thermore, it presents a hardware-based CMOS image sensor capable of real-time edge image<br>extraction, enhancing computational efficiency while reducing latency.<br>As we embark on this intellectual journey, we invite the reader to delve deeper into the<br>realms of emerging technologies, energy-efficient communication, and in-sensor computing.</p><p dir="ltr">By the culmination of this thesis, it is our hope that the insights garnered from this re-<br>search will empower emerging technologies, inspire further innovation, and usher in a more<br>sustainable and technologically empowered future.</p>

This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text

<p>In recent years, switch-mode power electronic converters have gained considerable popularity</p> <p>because of their compact size and high switching frequencies. This makes them</p> <p>suitable for power processing in various applications, including photovoltaic systems and</p> <p>electric vehicles. However, their high switching frequency capabilities have a drawback. A</p> <p>high-frequency common-mode voltage coupled with the switching of the power converters</p> <p>excites the parasitic capacitances of the system. It leads to the flow of common-mode current.</p> <p>Since the common-mode current flows through an unintended path, it can potentially</p> <p>interfere with the performance of system components. Passive filters can be used to mitigate</p> <p>common-mode currents. Using a common-mode inductor in conjunction with strategically</p> <p>placed capacitors makes it possible to limit the flow of common-mode current.</p> <p><br></p> <p>As part of this work, passive mitigation of common-mode current will be investigated in</p> <p>a variable frequency drive system. In this regard, the process of designing a three-phase ac</p> <p>common-mode inductor is explained. As a first step, a mitigation strategy is proposed and</p> <p>described. Next, the issue of self-capacitance of the inductor is discussed. Afterwards, the</p> <p>ac common-mode inductor is designed using a multi-objective optimization-based approach.</p> <p>Following this are the design results, concluding the dissertation.</p>

<p dir="ltr">Due to the rapidly evolving landscape of the Internet of Things (IoT), efficient<br>communication solutions are increasingly sought after. The thesis delves into<br>the development and validation of two optical communication systems (IDC,<br>2021). Capitalizing on the benefits of Optical Wireless Communication (OWC)<br>and Optical Frequency Identification(OFID), two innovative optical systems are<br>introduced: a single-pixel OFID optical reader and a computer vision-based<br>communication system that utilizes an OLED tag, a camera, and a laptop as a<br>reader. These systems are designed to surpass the challenges associated with<br>existing technologies like RFID and Bluetooth, offering enhancements in<br>security, privacy, and autonomy through the integration of energy harvesting<br>technologies. Moreover, the practical application of these systems in real-world<br>settings, such as animal and object identification, highlight their versatility<br>and potential for diverse IoT applications. The prototypes presented were<br>systematically developed and subjected to a series of evaluations to assess their<br>performance. These tests focused on measuring the communication distance<br>achieved, the power consumption of the devices, and the accuracy of data<br>transmission. The experiments demonstrated the technical feasibility of the<br>systems in real IoT environments, affirming their effectiveness in overcoming<br>distance limitations and energy efficiency challenges and providing an<br>alternative solution for accurate data transmission in environments where radio<br>communications cannot operate. These findings underscore the significance and<br>applicability of optical communications.<br>highlight<br></p>

<p dir="ltr">Sensing and communication circuits and systems are crucial components in various electronic devices and technologies. These systems are designed to acquire information from the surrounding environment through sensors, process that information, and facilitate communication between different devices or systems. It plays a vital role in modern electronic devices, enabling them to collect, process, and exchange information to perform various functions in applications such as IoB (Internet of Body), healthcare, hardware security, industrial automation, and more.</p><p dir="ltr">This work focuses on innovations in sensing and communication circuits spanning two independent application areas – human body communication and hardware emanations security.</p><p dir="ltr">First, an ultra-low power ECG monitoring system is implemented to perpetually power itself using Thermoelectric Generator (TEG) to harvest body energy while securely transmitting sensed data through on-body communication, achieving closed-loop operation without external charging or batteries. Custom circuits allow demonstrated feasibility of self-sustaining wearables leveraging Human Body Communication’s advantages.</p><p dir="ltr">Second, investigations reveal vulnerabilities introduced when repairing broken cables, with unintended monopole antennas boosting electromagnetic emissions containing signal correlations. Experiments characterize long-range detection regimes post-repair across USB keyboard cables. Further circuit and structural innovations provide localized shielding at repair points as a potential mitigation. Advancements offer contributions in understanding hardware emission security risks to inform protection strategies.</p><p dir="ltr">The two separate research work demonstrate specialized circuits advancing the state-of-the-art in sensing and communication for wearable body-based systems and hardware security through greater awareness of vulnerabilities from unintended emissions.</p><p><br></p>

<p dir="ltr">The demand for renewable energy and electric vehicles (EVs) is increasing, necessitating efficient energy conversion and management solutions. The thesis addresses the critical challenge of dynamically converting multiple Direct Current (DC) inputs to multiple DC outputs while maintaining efficiency and scalability. The primary objective is to design and test a Multi Input Multi Output (MIMO) DC converter, focusing on verifying its scalability and load efficiency. The research investigates hardware requirements, the implementation of multiphase circuits, and the balancing of power between various inputs through multistage cycling. The study hypothesizes that multistage cycling balances the output power between inputs, and multiphase configurations can scale the converter without affecting efficiency. Methods include examining existing converters, simulating multistage circuits, and fabricating a prototype. Key deliverables include a working prototype demonstrating scalability and efficiency. Results indicate that the MIMO DC converter performs efficiently with multiple inputs and outputs, achieving over 90% efficiency. The use of Gallium Nitride (GaN) transistors and synchronous buck converter topology proves effective in minimizing losses and enhancing stability. The research holds significant value in advancing renewable energy and DC converter technology, promoting sustainability and efficient energy management. Future work should explore advanced filtration circuits, higher voltage testing, and more complex configurations to further enhance the converter's capabilities.</p>

<p dir="ltr">Porous silicon (po-Si) is a unique form of silicon (Si) that features tunable nanopores distributed throughout its bulk structure. While crystalline Si (c-Si) already boasts technological advantages, po-Si offers an additional key aspect with its large surface area relative to its small volume, making it highly conducive to surface chemistry. In this research, our focus centers on the design of a synaptic device based on po-Si, exploring its potential for neuromorphic hardware applications.</p><p><br></p><p dir="ltr">To begin, we delve into the analysis of several electrical properties of po-Si using density functional theory (ab initio/first principles) calculations. Notably, we discover the presence of intra-pore dangling states within the bandgap region of po-Si. Although po-Si is known for its higher bandgap compared to c-Si, resulting in low carrier density and increased resistance, the existence of these dangling states significantly impacts its electronic transport.</p><p><br></p><p dir="ltr">Additionally, we investigate the electric-field driven modulation of dangling bonds through controlled intra-pore Si-H bond dissociation. This modulation enables precise control over the density of dangling states, facilitating the tunability of po-Si conductance. Theoretically evaluating the current-voltage characteristics of our proposed po-Si based synaptic devices, we determine the potential range of obtainable conductivity.</p><p><br></p><p dir="ltr">Finally, we evaluate the performance by integrating porous silicon nanoelectronics devices into neural networks. These devices exhibit superior synaptic plasticity, faster response times, and reduced power consumption compared to other synapses. The research indicates that poroussilicon devices are highly effective in neuromorphic systems, paving the way for more efficient and scalable neural networks. These advancements have significant practical and cost-effective implications for a wide range of applications, including pattern recognition, machine learning, and artificial intelligence.</p><p><br></p><p dir="ltr">Overall, our analyses reveal that the integration of po-Si based synaptic devices into the neural fabric offers a path towards achieving significantly denser and more energy-efficient neuromorphic hardware. With its tunable properties, large surface area, and potential for controlled conductance, po-Si emerges as a promising candidate for the development of advanced silicon based nano-electronic devices tailored for neuromorphic computing. As we delve deeper into the potentials of po-Si, the era of cognitive computing, inspired by the elegance of bio-mimetic neural networks, edges closer to becoming a reality.<br><br></p>