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<p>    </p> <p>An energy harvesting system (EHS) provides the intriguing possibility of battery-less computing and enables various applications such as wearable, industrial or environmental sensors, and im- plantable medical devices. The biggest challenge of EHS is the instability of energy sources (e.g., Wi-Fi, solar, thermal energy, etc.) which causes unpredictable and frequent power outages. To address the challenge, existing works introduce software-based and hardware-based power failure recovery solutions that ensure program correctness across a power outage. However, they cause a significant performance overhead without providing the high quality of service in reality, and suffer from a reliability issue. In this dissertation, we address the limitations of recovery solutions across the system stack, from the compiler-directed approach and run-time systems to hardware mechanisms, and demonstrate the effectiveness of the approaches using real EHS platforms and simulators. We first present software-based recovery solutions by leveraging compiler support. We develop a compiler-directed solution built upon commodity EHS platform that can achieve 3X speedup compared to the software-based state-of-the-art solution. We also introduce a compiler optimization technique that can cooperate with run-time systems and hardware support, achieving 8X speedup compared to the software-based solution. We then present hardware-based recov- ery solutions by leveraging compiler and hardware support. We develop an architecture/compiler co-design solution that re-purposes existing hardware components in a core for power failure spec- ulative execution, a new speculation paradigm, and leverages a novel compiler analysis for cor- rect power failure recovery. Our result highlights 2 ∼ 3x performance improvement compared to the hardware-based state-of-the-art solution without requiring hardware modification. Next, we present a new cache design for EHS that can achieve cost-effective, high-performance intermit- tent computing. According to experimental results, the new cache design outperforms the state- of-the-art cache scheme by 4X and reduces the hardware cost by 90%. Finally, we present an operating system (OS)-driven solution to address a reliability problem on EHS devices while all existing works are vulnerable, causing the wrong recovery across power failure. Our experiments demonstrate that the solution causes less than 1% run-time overhead and successfully addresses the reliability problem without compromising correct power failure recovery. </p>

Agda is a dependently-typed programming language and theorem prover, supporting proof construction in a functional programming style. Due to its incredibly flexible concrete syntax and support for Unicode identifiers, Agda can be used to construct elegant and expressive proofs in a format that is understandable even to those unfamiliar with the tool. However, the semantics of Agda is lacking resource guarantees of the kind that Haskell programmers are used to with lazy evaluation, where multiple uses of function arguments and let-bound variables still result in the corresponding expressions to be evaluated at most once. With the current compiler backends of Agda, a mathematically-natural way to structure programs therefore frequently results in inefficient compiled programs, where the run-time complexity can be exponentional in cases where corresponding Haskell code executes in linear time. This makes a highly-optimised compiler backend a particularly essential tool for practical development with Agda. The main contributions of this thesis are a series of compiler optimisations that inlines simple projections, removes some expressions with trivial evaluations that can be statically inferred, and reduces the need for repeated evaluations of the same expressions by increasing sharing. We developed transformations that focus on the inherent “loss” of sharing that is frequently the result of compiling Agda programs. Where an Agda developer may imagine that value sharing should exist in the generated Haskell code, it often does not. We present several optimising transformations that re-introduce some of this “lost” sharing without affecting the type-theoretic semantics, then apply these optimisations to several typical Agda applications to examine the memory allocation and execution time effects. In measuring the effects of these optimisations on Agda code we show that overall improvements in runtime on the order of 10-20% are possible. We hope that the development and discussion of these optimisations is useful to the Agda developer community, and may be helpful for future contributors interested in implementing new optimisations for Agda. / Thesis / Master of Science (MSc)

Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption. Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion. / Master of Science

Communication in microkernel-based systems is much more frequent than system calls known from monolithic kernels. This can be attributed to the placement of system services into their own protection domains. Communication has to be fast to avoid unnecessary overhead. Also, communication channels in microkernel-based systems are used for more than just remote procedure calls. In distributed systems, which also have a componentized design, it is state of the art to use tools to generate stubs for the communication between components. The communication interfaces of components are described in an interface definition language (IDL). In contrast to distributed systems, components of a microkernel-based system run on the same architecture and message delivery is guaranteed. In this Thesis, I explore the different kinds of communication, which can be used in microkernel-based systems, as well as their possible representation in IDL. Specifically, I introduce the syntax to describe kernel objects in IDL. I discuss the complexity of IDL compilers and its relation to the complexity of the IDL. Furthermore, I evaluate the performance of the communication stubs generated by different IDL compilers and discuss techniques to minimize performance overhead in generated stubs. I validated these techniques by implementing the Drops IDL Compiler - Dice. Finally, this Thesis presents a mechanism to measure the frequency and performance of invocations of generated communication code. I used this technique to conduct measurements in highly complex systems and introducing the least possible overhead.

Communication in microkernel-based systems is much more frequent than system calls known from monolithic kernels. This can be attributed to the placement of system services into their own protection domains. Communication has to be fast to avoid unnecessary overhead. Also, communication channels in microkernel-based systems are used for more than just remote procedure calls. In distributed systems, which also have a componentized design, it is state of the art to use tools to generate stubs for the communication between components. The communication interfaces of components are described in an interface definition language (IDL). In contrast to distributed systems, components of a microkernel-based system run on the same architecture and message delivery is guaranteed. In this Thesis, I explore the different kinds of communication, which can be used in microkernel-based systems, as well as their possible representation in IDL. Specifically, I introduce the syntax to describe kernel objects in IDL. I discuss the complexity of IDL compilers and its relation to the complexity of the IDL. Furthermore, I evaluate the performance of the communication stubs generated by different IDL compilers and discuss techniques to minimize performance overhead in generated stubs. I validated these techniques by implementing the Drops IDL Compiler - Dice. Finally, this Thesis presents a mechanism to measure the frequency and performance of invocations of generated communication code. I used this technique to conduct measurements in highly complex systems and introducing the least possible overhead.

The Swedish Armed Forces are currently considering extending the operational life of the Saab JAS 39 Gripen C/D multirole fighter aircraft by an additional 10 to 20 years. This has resulted in a need to upgrade many of the hardware components originally developed in the late 1980s and early 1990s. These upgrades include the Application Specific Integrated Circuits (ASICs) used to generate graphics in the aircraft’s Cockpit Display System (CDS), made programmable through the Symbol Programming Language (SPL). SPL is a proprietary Domain Specific Language (DSL) developed specifically to be used with the custom hardware in the Gripen’s CDS. An upgrade of the underlying hardware would necessitate migrating the old SPL software to some other format suitable for modern hardware. Large parts of this process could be automated with the help of a source-to-source compiler, i.e., a transpiler. In this thesis, we present a translation-verifying transpiler for a subset of SPL, dubbed μSPL, that outputs equivalent OpenGL/C++ programs. Verification is done at runtime against a reference program execution trace produced by the transpiler by means of symbolic execution in the operational semantics of μSPL. An observational study was made to evaluate the solution and the soundness of the μSPL semantics. From the results of the observational evaluation, we find that the chosen method for translation verification is contextually suitable, albeit with potential for improvement in the details of the implementation. / Försvarsmakten överväger i skrivande stund att förlänga tjänsteperioden för enhetflygplanet Saab JAS 39 Gripen C/D med ytterligare 10 till 20 år. Detta har resulterat i ett behov av att uppgradera många av de hårdvarukomponenter som ursprungligen togs fram för Gripenprojektet under sena 1980-talet och tidiga 1990-talet. Dessa uppgraderingar inkluderar applikationsspecifika integrerade kretsar (ASIC:ar) som används för att driva och generera symbolik för presentationssystemet Elektroniskt Presentationssystem 17 (EP-17) i cockpit på Gripen C/D. Dessa ASIC:ar är programmerbara med det egenutvecklade grafikprogramspråket SPL. En uppgradering av den underliggande hårdvaran skulle nödvändiggöra en migration av den SPL-mjukvara som redan är skriven till något format som är lämpligt för modern hårdvara. Stora delar av den här processen skulle kunna automatiseras med en automatisk översättare; en så kallad transpilator. I den här avhandlingen presenterar vi en översättningsverifierande transpilator för en delmängd av SPL, kallad μSPL, som översätter till ekvivalenta OpenGL/C++ program. Verifiering görs under körning mot ett exekveringsspår (execution trace) som producerats av transpilatorn parallellt med översättningen med hjälp av symbolisk exekvering i den operationella semantiken för μSPL. En observationell studie görs för att utvärdera lösningen och sundheten hos den använda μSPL-semantiken. Från den observationella studien framgår det att den föreslagna metoden för översättningsverifikation är lämplig i sammanhanget, med utrymme för förbättring i implementationsdetaljerna.