The development of radio frequency integrated circuits (RFICs), especially the dream of integrating analog, digital and radio frequency (RF) components on the same chip that is commonly known as System-on-a-Chip (SoC), is crucial to mobile communications of the future. Such SoC approach offers enhanced performance, greater reliability, and substantially less power consumption of integrated circuits while reducing overall physical size and thus manufacturing cost. However, the progress has been stalled by the lack of miniaturized inductor elements. Rise of unwanted parasitic effects limits down-scaling of the inductor structures and leaves the use of magnetic coating as a viable and attractive option to enhance the inductance and thus inductance density. It is also essential to shift from perm alloy and other amorphous alloys to ferrites and hex ferrites as the core material because of their very high electrical resistivity so as to keep losses in check, a criterion that cannot be compromised on in GHz frequency applications. This is viable, however, only if the integration of the magnetic core (film), particularly a ferrite film, is fully compatible with the CMOS fabrication process. Various approaches have been taken to meet this requirement, including investigations of employing layers of ferrite materials to envelop the inductor loop. However, the deposition of thin films of ferrites, whether by PVD or CVD, usually calls for the deposited ferrite layer to be annealed at an elevated temperature to crystallize the layer so that its magnetic characteristics are appropriate for the optimum performance of the circuit element. Such annealing is incompatible with CMOS process flow required for aggressive device geometries, as the inductor element is added after the active semiconductor circuit is processed, and any exposure of the processed circuit to elevated temperatures risks disturbing precise doping profiles employed and the integrity of the inter-layer dielectrics. What is called for is a low-temperature process for the deposition of a ferrite layer on top of the patterned inductor element – a layer of thickness such that most of the fringe field is encapsulated – while ensuring that the layer comprises crystallites of uniform size that leads to uniform magnetic behaviour. Recognizing the difficulty of meeting the various stringent requirements, it has recently been remarked that such a goal is a formidable challenge. In an attempt to address this challenge, in this work, we have adopted a counter-intuitive approach - the deposition of the desired ferrite composition on a processed die (that contains the inductor structures along with active semiconductor circuits) by immersing it into a chemical (reactant) solution, followed by a brief irradiation of microwave frequency. However, to identify the desired ferrite composition and the appropriate recipe to deposit them, a systematic effort had to be made first, to understand the inter-relationship between synthesis process, structure of resulting material, and its physical and chemical properties. Therefore, at the beginning, a general introduction in which key concepts related to the magnetic-core inductors, the microwave-irradiation-assisted synthesis of nanostructures, the ‗state of the art‘ in the field of integration of appropriate magnetic material to the RFICs, are all outlined. As a proof of concept, microwave-irradiation-assisted solution-based deposition of zinc ferrite thin films on the technologically important Si (100) substrate is demonstrated. The highlight of the process is the use of only non-toxic metal organic precursors and aqua-alcoholic solvents for the synthesis, which is complete in 10 minutes @< 100 °C, without any poisonous by-products. Effects of various process parameters such as solute concentrations, surfactant types, and their concentrations are investigated. A wide range of deposition rates (10 - 2000 nm/min) has been achieved by tweaking the process parameters. The simultaneous formation of zinc ferrite nanocrystallites (ZFNC) along with deposition of thin film is the hallmark of this synthesis technique. Unlike its bulk counterpart, both film and powder are found upon investigation to be rich in magnetic behavior– owing to plausible cationic distribution in the crystal lattice, induced by the inherently quick and far-from-equilibrium nature of the process. The accurate estimation of magnetic characteristics in film is, however, found to be difficult due to the high substrate-to-film mass ratio. The simultaneously prepared ZFNC is examined to arrive at the optimized process recipe that imparts the desired magnetic properties to the zinc ferrite system. The crystallographic cationic distribution in zinc ferrite powder is, however, difficult to study due to the nanoscale dimension of the as prepared material. To enable crystal growth, slow and rapid annealing in air at two different temperatures are employed. The effects of these annealing schemes on various attributes (magnetic properties in particular) are studied. Rapid annealing turns out to be an interesting pathway to promote rapid grain-growth without disturbing the crystallographic site occupancies. The presence of inversion, i.e., the amount of Fe3+ in the ‗A‘-sites in the spinel structure that ideally is zero in normal spinel structure of zinc ferrite, is evident in all annealed ZFNC, as determined by Riveted analysis. Such partially inverted ZFNC exhibits soft magnetic behavior with high saturation magnetization, which can easily be ―tuned‖ by choosing appropriate annealing conditions. However, a few unique strategic modifications to the same microwave-irradiation-assisted solution-based synthesis technique are tried for the formation of nanocrystalline powder with desired sizes and properties without the necessity of anneal. The approach eventually appears to pave a way for the formation of oriented structures of zinc ferrite. The effects of anneal, nevertheless, are studied with the help of neutron powder diffractometry and magnetic measurements. The magnetic ordering at various temperatures is analyzed and connected to the magnetic measurements. The study shows that long-range magnetic ordering, present even at room temperate, originates from the distribution of cations in the partially inverted spinel structures, induced by the rapid and kinetically driven microwave synthesis. Keeping the mild nature (<200 °C) of the processing in mind, a large degree of inversion (~0.5) is a surprise and results in a very high saturation magnetization, as much as 30 emu/g at room temperature (paramagnetic in bulk), in the ZFNC system. Based on the knowledge of process-structure-property interrelationship, a recipe for the deposition of ferrite thin films by the microwave-assisted deposition technique is optimized. Successful deposition of smooth and uniform zinc ferrite thin films on various substrates is, then, demonstrated. The mystery behind the strong adherence of the film to the substrate - an unexpected outcome of a low-temperature process - is probed by XPS and the formation of silicates at the interface is identified as the probable reason. The uniformity and consistency of film composition is also examined in this chapter. Another salient feature of the process is its capability to coat any complex geometry conformally, allowing the possibility of depositing the material in a way to ―wrap around‖ the three-dimensional inductor structures of RF-CMOS. Integration of nanostructure zinc ferrite thin films onto on-chip spiral inductor structures has been demonstrated successfully. The magnetic-core inductors so obtained exhibit the highest inductance density (700 nH/mm2) and the highest Q factor (~20), reported to date, operate at 5 GHz and above, by far the highest reported to date. An increase in inductance density of as much as 20% was achieved with the use of just 1 µm thick film of zinc ferrite covering only the ―top‖ of the spiral structure, i.e., up to 20% of chip real estate can potentially be freed to provide additional functionality. The microwave-assisted solution-based deposition process described in this thesis is meant for ‗post-CMOS‘ processing, wherein the film deposited on some specific electronic components can add desired functionality to or improve the performance of a component (circuit) underneath. However, the effect of such ‗post-CMOS‘ processing on the active MOS devices, interconnects, and even inter-layer-dielectrics fabricated prior to the deposition has to be mild enough to leave the performance of delicate MOS characteristics intact. Such CMOS-compatibility of the present deposition process has been tested with a satisfactorily positive result.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text

Recently, high-κ materials have become the focus of research and been extensively utilized as the gate dielectric layer in aggressive scaled complementary metal-oxide-semiconductor (CMOS) technology. Hafnium dioxide (HfO2) is the most promising high-κ material because of its excellent chemical, thermal, mechanical and dielectric properties and also possesses good thermodynamic stability and better band offsets with silicon. Hence, HfO2 has already been used as gate dielectric in modern CMOS devices. For future technologies, it is very difficult to scale the silicon transistor gate length, so it is a necessary requirement of replacing the channel material from silicon to some high mobility material. Two-dimensional layered materials such as graphene and molybdenum disulfide (MoS2) are potential candidates to replace silicon. Due to its planar structure and atomically thin nature, they suit well with the conventional MOSFET technology and are very stable mechanically as well as chemically. HfO2 plays a vital role as a gate dielectric, not only in silicon CMOS technology but also in future nano-electronic devices such as graphene/MoS2 based devices, since high-κ media is expected to screen the charged impurities located in the vicinity of channel material, which results in enhancement of carrier mobility. So, for sustenance and enhancement of new technology, extensive study of the functional materials and its processing is required. In the present work, optimization of HfO2 thin films for gate dielectric applications in Nano-electronic devices using electron beam evaporation is discussed. HfO2 thin films have been optimized in two different thickness regimes, (i) about 35 nm physical thicknesses for back gate oxide graphene/MoS2 transistors and (ii) about 5 nm physical thickness to get Equivalent Oxide Thickness (EOT) less than 1 nm for top gate applications. Optical, chemical, compositional, structural and electrical characterizations of these films have been done using Ellipsometry, X-ray Photoelectron Spectroscopy (XPS), Rutherford Back Scattering (RBS), X-ray Diffraction (XRD), Capacitance-Voltage and Current-Voltage characterization techniques. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post deposition annealing (PDA) and post metallization annealing (PMA) in forming gas ambient (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. A high density film (ρ=8.2 gram/cm3, 85% of bulk density) with high dielectric constant of κ=19 and leakage current density of J=2.0×10-6 A/cm2 at -1 MV/cm has been achieved at optimized deposition conditions. Bilayer graphene on HfO2/Si substrate has been successfully identified and also transistor has been fabricated with HfO2 (35 nm) as a back gate. High transconductance compared to other back gated devices such as SiO2/Si and Al2O3/Si and high mobility have been achieved. The performance of back gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 SCCM and 20 SCCM has been evaluated. It is found that the device on the film deposited at 3 SCCM O2 flow rate shows better properties. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. MoS2 layers on the optimized HfO2/Si substrate have been successfully identified and transistor has been fabricated with HfO2 (32 nm) as a back gate. The device is switching at lower voltages compared to SiO2 back gated devices with high ION/IOFF ratio (>106). The effect of film thickness on optical, structural, compositional and electrical properties for top gate applications has been studied. Also the effect of gate electrode material and its processing on electrical properties of MOS capacitors have been studied. EOT of 1.2 nm with leakage current density of 1×10-4 A/cm2 at -1V has been achieved.

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms. Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100). Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity. In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely: (a) Sub-threshold based sensing (b) Fringe field based sensing and (c) Tunneling current based sensing. a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out. For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored. CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF. b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored. c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.