No description available.

No description available.

Reducing the computing time of the matrix inversion has been a concern of many authors. The use of Systolic architectures containing orthogonally connected processing elements capable of few instructions multiple data have allowed for new algorithms to be implemented. Two algorithms are examined that rely on the triangularization methods for matrix inversion. One can be applied to the general non-singular matrix and the other to the symmetric matrix. The throughput in both implementation is revolutionized. The speed improvement over Liu and Young’s implementation of the symmetric matrix inversion is by a factor of three. The throughput in both implementation is revolutionized. The speed improvement over Liu and Young’s implementation of the symmetric matrix inversion is by a factor of three.

<p>    </p> <p>An energy harvesting system (EHS) provides the intriguing possibility of battery-less computing and enables various applications such as wearable, industrial or environmental sensors, and im- plantable medical devices. The biggest challenge of EHS is the instability of energy sources (e.g., Wi-Fi, solar, thermal energy, etc.) which causes unpredictable and frequent power outages. To address the challenge, existing works introduce software-based and hardware-based power failure recovery solutions that ensure program correctness across a power outage. However, they cause a significant performance overhead without providing the high quality of service in reality, and suffer from a reliability issue. In this dissertation, we address the limitations of recovery solutions across the system stack, from the compiler-directed approach and run-time systems to hardware mechanisms, and demonstrate the effectiveness of the approaches using real EHS platforms and simulators. We first present software-based recovery solutions by leveraging compiler support. We develop a compiler-directed solution built upon commodity EHS platform that can achieve 3X speedup compared to the software-based state-of-the-art solution. We also introduce a compiler optimization technique that can cooperate with run-time systems and hardware support, achieving 8X speedup compared to the software-based solution. We then present hardware-based recov- ery solutions by leveraging compiler and hardware support. We develop an architecture/compiler co-design solution that re-purposes existing hardware components in a core for power failure spec- ulative execution, a new speculation paradigm, and leverages a novel compiler analysis for cor- rect power failure recovery. Our result highlights 2 ∼ 3x performance improvement compared to the hardware-based state-of-the-art solution without requiring hardware modification. Next, we present a new cache design for EHS that can achieve cost-effective, high-performance intermit- tent computing. According to experimental results, the new cache design outperforms the state- of-the-art cache scheme by 4X and reduces the hardware cost by 90%. Finally, we present an operating system (OS)-driven solution to address a reliability problem on EHS devices while all existing works are vulnerable, causing the wrong recovery across power failure. Our experiments demonstrate that the solution causes less than 1% run-time overhead and successfully addresses the reliability problem without compromising correct power failure recovery. </p>

Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16694

Modern parallel computing techniques are subject to poor scalability. Their performance tends to suffer diminishing returns and even losses with increasing parallelism. Some methods of intelligent computing, such as neural networks and genetic algorithms, lend themselves well to massively parallel systems but come with other drawbacks that can limit their usefulness such as the requirement of a training phase and/or sensitivity to randomness. This thesis investigates the feasibility of a novel method of intelligent parallel computing by implementing a true multiple instruction stream, single data stream (MISD) computing system that is theoretically nearly perfectly scalable. Computational dreaming (CD) is inspired by the structure and dreaming process of the human brain. It examines previously observed input data during a 'dream phase' and is able to develop and select a simplified model to use during the day phase of computation. Using mazes as an example problem space, a CD simulator is developed and successfully used to demonstrate the viability and robustness of CD. Experiments that focused on CD viability resulted in the CD system solving 15% of mazes (ranging from small and simple to large and complex) compared with 2.2% solved by random model selection. Results also showed that approximately 50% of successful solutions generated match up with those that would be generated by algorithms such as depth first search and Dijkstra's algorithm. Experiments focusing on robustness performed repeated trials with identical parameters. Results demonstrated that CD is capable of achieving this result consistently, solving over 32% of mazes across 10 trials compared to only 3.6% solved by random model selection. A significant finding is that CD does not get stuck on local minima, always converging on a solution model. Thus, CD has the potential to enable significant contributions to computing by potentially finding elegant solutions to, for example, NP-hard or previously intractable problems. / Master of Science

Most computationally-intensive programs spend a majority of their time within a small portion of the executable code. A novel computer architecture and compiler, called PRISM-2, is introduced, which improves the performance of these programs by synthesizing the "most often" executed instructions. This is accomplished by augmenting a general-purpose processor with an array of FPGAs. The information regarding the structures to be synthesized is extracted from the high-level language (HLL) specification presented at the input of the PRISM-2 compiler. This behavioral specification is transformed into an internal, dataflow graph (DFG) format. Linear and loop optimizations are then performed to optimize this representation. Linear optimizations are the main topic of discussion in this thesis. The optimized DFG is then synthesized on the reconfigurable platform. / Master of Science

Recent advances in VLSI technology have stimulated research efforts in the area of highly reliable fault tolerant, general purpose computing systems, notably, parallel systems. An automatically reconfigurable, fault-tolerant, parallel architecture is suited to VLSI technology. The architecture, a uniformly interconnected array of identical cells, is capable of functional reconfiguration as well as fault reconfiguration. Microprocessor cells are suggested as the "fabric" for implementation of the array. This thesis also introduces an I/O algorithm as an extension to the reconfiguration process, and outlines the steps by which the array cells construct paths from the active-array to the cellular array I/O ports. Path reconfiguration is presented as the method by which fault-free paths replace faulty paths. A testing algorithm is described for use in the self-testing operation of the array. The types of tests that are conducted on cells are outlined, and the basis by which a cell determines the faulty or fault-free status of a cell is described. / M.S.

Dynamic hierarchical networks represent an architectural strategy for employing adaptive behavior in applications sensitive to highly variable external demands or uncertain internal conditions. The characteristics of such architectures are described, and the significance of adaptive capability is discussed. The necessity for assessing cost/benefit tradeoffs leads to the use of queueing network models. The general model, a network of M/M/1 queues in a random environment, is introduced and then is simplified so that the links may be treated as isolated M/M/1 queues in a random environment. This treatment yields a formula for approximate mean network delay by combining matrix-geometric results (mean queue length and mean delay) for the individual links. Conditions under which the analytic model is considered valid are identified through comparison with a discrete event simulation model. Last, performance of the dynamic hierarchy is compared with that of the static hierarchy. This comparison establishes conditions for which the dynamic architecture enables performance equal or nearly equal to performance of the static architecture. / Ph. D. / incomplete_metadata

Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending energy, using up battery life. Increasing power consumption is a rising concern to users and researchers alike. Power gating, turning off a blocks of hardware when idle, reduces static power consumption. The Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) currently employed in processors leak current. Even in power gated circuits, MOSFET power gating may only save between 60-80% of power. A different type of switch, a Nanoelectromechanical Systems (NEMS) switch, presents an air gap between the source and drain while in the off state, eliminating subthreshold leakage current. The NEMS switch is slower to operate and only has a finite number of switching before breaking. They should be switched with caution. Proposed in this thesis is a hybrid power gating model wherein a MOSFET is placed in series with a NEMS switch. Power gating the Floating Point Unit (FPU) of a processor is studied through the use of modern open source computer architecture simulators. Each switch type is used to model power gating to observe energy savings and performance costs. The hybrid power gating model is more flexible across a variety of applications. Energy savings are comparable to single NEMS switch power gating for applications with low FPU activity. Any performance loss remains low, matching that of MOSFETs. Processor electrical costs are heavily reduced while devices remain operating at a near-optimal speed. / Master of Science / Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external input. During this time, they are expending energy, using up battery life. The transistors that are inside of them, the minuscule electronics that make these devices work, are not perfect and “leak” current even when not in use. Another type of switch, a mechanical one, has been under development over the last decade. This mechanical switch is slower to operate and is not as reliable as current transistors yet yields a complete disconnection when turned off. Thus, no energy is wasted when a device is sitting idle. While this saves more energy, using a mechanical switch also has the potential to degrade a device’s performance due to its slow operation. In this thesis, the effectiveness of combining the two types of transistors into one process is analyzed. The fast switching times of the currently used transistors can be used in situations where it is difficult to determine whether shutting down a piece of hardware is a good decision. If it has been determined that the circuit may be put to sleep for a long amount of time, the slower but more energy efficient mechanical switch may be used. With this hybrid operation, each transistor is only used in a mode that suits them most appropriately.