abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019

This thesis presents the fundamental issues of the digital controlled DC/DC converter. A lot of challenges exist when you introduce the digital control technique into the control of the DC/DC converter, especially with regards to the voltage regulator module. One issue is the limit cycle oscillation problem caused by the quantization effect from the ADC and DPWM of the digital control chip. Another issue is the delay problem coming from the sample-hold effect. In this thesis, the modeling, analysis and design methodology for the constant frequency voltage-mode control is reviewed. A DPWM (Digital Pulse Width Modulator) model is verified in simulation, which shows what effects the digital control brings to the conventional Pulse Width Modulator. In CPES, the constant on-time control concept is introduced into the digital control of the voltage regulator module. This provides a high resolution of DPWM and allows the digital constant on-time voltage-mode control architecture to be proposed. To limit the oscillation amplitude in the digital control structure, the digital constant on-time current-mode control w/ external ramp is further proposed in CPES. To analyze this structure, a describing function model is proposed for the digital constant on-time current-mode control, which takes both the sample-hold effect and the quantization effect into consideration. This model clearly shows the stability problem caused by the sample-hold effect in the current loop. Using larger ramp's slope values, this stability issue can be alleviated. Based on this model, a design methodology is introduced. By properly designing the current loop's ADC resolution and the voltage loop's ADC resolution, the limit cycle oscillation in this structure can be minimized: the digital constant on-time current-mode control will only have the oscillation coming from the sample-hold effect in the current loop, which can be greatly reduced by adding the large slope's external ramp to this structure. Simulation verification for this design methodology is provided to prove the concepts. Based on the proposed model, the compensator design is performed. The motivation for the compensator design is to push the bandwidth while satisfying the stability condition and the dynamic no-limit-cycle oscillation condition. When analyzing the case of one sample per switching cycle, there is a certain amount of delay, which compromises the phase characteristics. Our design also requires a large external ramp because it will reduce the oscillation amplitude in our system. From our model, it is quite obvious that the external ramp must have a slope larger than one time that of inductor current down slope. A slope that is too larger will weaker the phase and limit the bandwidth. When using the normal current-mode compensator, like the 1-pole 1-zero compensator, the phase is dropped too much and the bandwidth will be limited too low. If we use a 2-pole 2-zero compensator, the phase can be boosted. However, in this case, the gain margin requirement from the dynamic no-limit-cycle oscillation condition will make the further improvements on bandwidth impossible. In our design, the one sixth of the switching frequency is achieved. / Master of Science

In this thesis, the possibility of applying digital current mode control on multiple-input (MI) converters is studied. As for MI topologies having a central energy transfer inductor, the predictive constant on-time current-mode control can greatly reduce both the design and digital realization efforts needed. By doing digital constant on-time current-mode control, the control of MI buck and MI buck-boost converters can be simplified into an equivalent-single-input converter control problem. The small signal models of digital constant on-time controlled single-input (SI), MI buck and SI, MI buck-boost converters in both CCM and DCM are proposed. Simulations and experiments were built to verify the proposed models. / text

The data center serves as the hardware foundation for artificial intelligence (AI) and cloud computing, constituting a global market that has surpassed $200 billion and is experiencing rapid growth. It is estimated that data centers contribute to 1.7-2.2% of the world's electricity generation. Conversely, up to 80% of the long-term operational expenditure of data centers is allocated to electricity consumption. Consequently, enhancing the efficiency of electric energy conversion in data centers is not only economically advantageous but also crucial for achieving carbon-neutral objectives. Through collaborative efforts between the industrial and academic sectors, substantial advancements have been achieved in the energy conversion efficiency of data centers. Most converters within the data center power architecture now boast efficiencies exceeding 99%. However, the bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs), given their heightened power demands compared to conventional central processing units (CPUs). To enhance system efficiency, a revolutionary shift in power architecture has been introduced, advocating for the adoption of a 48 V data center power architecture to replace the conventional 12 V architecture. The higher 48 V bus voltage significantly reduces distribution loss on the bus. However, the primary challenge lies in managing high step-down voltage conversion while maintaining high efficiency. Additionally, high-performance microprocessors, including CPUs, GPUs, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), require hundreds of amperes of current at low voltage levels (e.g., GPUs need >220 A at <1.85 V, CPUs need >1000 A at <1.0 V). An unavoidable consequence of upscaling processor current and size is the substantial resistive loss in VRMs. This is because such loss scales with the square of the current [I2R], and the power path area (and resistance R) expands with the processor size. The Power Delivery Network (PDN) resistance in the "last inch" of the power delivery path is becoming a limiting factor in processor performance and system efficiency. The key to reducing the I2R loss is minimizing the distance between the VRMs and processors by utilizing ultra-high power density VRMs. Furthermore, the design of Voltage Regulator Modules (VRMs) for high-performance microprocessors encounters additional formidable challenges, especially when dealing with the requirements of contemporary computing architectures. The key hurdles encompass achieving high efficiency, handling low output voltage, accommodating wide voltage ranges, managing elevated output currents, and addressing significant load transients. These challenges prompt both academia and industry to explore novel topologies, innovative magnetic integration methods, and advanced control strategies. The prevailing trend in state-of-the-art 48V solutions centers around the adoption of two-stage configurations, wherein the second stage can leverage conventional 12V solutions. However, this approach imposes limitations on power density and efficiency, given that power traverses two cascaded DC/DC converters. Additionally, the footprint of decoupling capacitors and I2R loss on the intermedia bus between the two stages is emerging as a noteworthy consideration in designs. In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. Initially, a single-stage coupled-transformer voltage regulator (CTVR) with discrete magnetics is presented, offering a 48V solution while maintaining a comparable size and cost to a state-of-the-art 12V multiphase buck regulator. Leveraging the indirect-coupling concept, magnetic components are standardized, enabling scalability and facilitating multiphase operation. A prototype is constructed and tested to validate the CTVR's performance. With a 48V input and 1.8V output, the peak efficiency registers at 92.1%, and the power area density is 0.45 W/mm2. However, voltage ringing is observed in both primary and secondary switches due to a larger leakage inductance and hard-switching operation. Subsequently, a transition to soft-switching operation is implemented to address the voltage ringing issue. The leakage inductance is intentionally designed to supply energy for zero-voltage switching (ZVS) of primary switches, turning the previously perceived drawback into an opportunity for efficiency improvement. As a result, testing demonstrates a peak efficiency increase of more than 1%, reaching 93.6%. Furthermore, efforts are made to enhance small leakage inductance by employing well-interleaved printed circuit board (PCB) windings. Following a series of design optimizations, the prototype achieves a peak efficiency of 93.1% and a remarkable power density of 1037 W/in3, accounting for gate driver loss and size. Despite an increase in cost associated with PCB windings, this proposed solution attains the highest power density and stands as the pioneering 48V single-stage design surpassing 1000 W/in3 power density. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results. / Doctor of Philosophy / Data center is the hardware foundation of artificial intelligence (AI) and cloud computing. The global data center market has exceeded $200 billion and is fast growing. It is estimated that data center accounts for 1.7~2.2% of the world's electricity generation. On the other hand, up to 80% of the long-term operation expenditure of data centers is electricity. Thus, improving the efficiency of electric energy conversion in data centers is economically beneficial and critical to reaching the carbon neutral goal. The bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs). In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results.

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application. The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range. The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance. / Master of Science

Recently, constant-on-time V2 control is more and more popular in industry products due to features of high light load efficiency, simple implementation and fast transient response. In many applications such as cell phone, camera, and other portable devices, low-ESR capacitors such as ceramic caps are preferred due to small size and small output voltage ripple requirement. However, for the converters with ceramic caps, the conventional V2 control suffers from the sub-harmonic oscillation due to the lagging phase of the capacitor voltage ripple relative to the inductor current ripple. Two solutions to eliminate sub-harmonic oscillations are discussed in [39] and the small-signal models are also derived based on time-domain describing function. However, the characteristic of constant-on-time V2 with external ramp is not fully understood and no explicit design guideline for the external ramp is provided. For digital constant on-time V2 control, the high resolution PWM can be eliminated due to constant on-time modulation scheme and direct output voltage feedback [43]. However, the external ramp design is not only related to the amplitude of the limit-cycle oscillation, but also very important to the stability of the system. The previous analysis is not thorough since numerical solution is used. The primary objective of this work is to gain better understanding of the small-signal characteristic for analog and digital constant-on-time V2 with ramp compensations, and provide the design guideline based on the factorized small-signal model. First, constant on-time current-mode control and constant on-time V2 control are reviewed. Generally speaking, constant-on-time current mode control does not have stability issues. However, for constant-on-time V2 control with ceramic caps, sub-harmonic oscillation occurs due to the lagging phase of the capacitor voltage ripple. External ramp compensation and current ramp compensation are two solutions to solve the problem. Previous equivalent circuit model extended by Ray Ridley's sample-and-hold concept is not applicable since it fails to consider the influence of the capacitor voltage ripple. The model proposed in [39] successfully considers the influence from the capacitor voltage ripple by using time-domain describing function method. However, the characteristic of constant-on-time V2 with external ramp is not fully understood. Therefore, more research focusing on the analysis is needed to gain better understanding of the characteristic and provide the design guideline for the ramp compensations. After that, the small-signal model and design of analog constant on-time V2 control is investigated and discussed. The small-signal models are factorized and pole-zero movements are identified. It is found that with increasing the external ramp, two pairs of double poles first move toward each other at half of switching frequency, after meeting at the key point, the two double poles separate, one pair moves to a lower frequency and the other moves to a higher frequency while keeping the quality factor equal to each other. For output impedance, with increasing the external ramp, the low frequency magnitude also increases. The recommended external ramp is around two times the magnitude at the key point K. When Duty cycle is larger, the damping performance is not good with only external ramp compensation, unless very high switching frequency is used. With current ramp compensation, it is recommended to design the current ramp so that the quality factor of the double pole is around 1. With current ramp compensation, the damping can be well controlled regardless of the circuit parameters. Next, the small-signal analysis and design strategy is also extended to digital constant on-time V2 control structure which is proposed in [43]. It is found that the scenario is very similar as analog constant on-time V2 control. The external ramp should be designed around the key point to improve the dynamic performance. The sampling effects of the output voltage require a larger external ramp to stabilize digital constant-on-time V2 control while suffers only a little bit of damping performance. One simple method for measuring control-to-output transfer functions in digital constant-on-time V2 control is presented. The experimental results verify the small-signal analysis except for the high frequency phase difference which reveals the delay effects in the circuit. Load transient experimental results prove the proposed design guideline for digital constant on-time V2 control. As a conclusion, the characteristics of analog and digital constant-on-time V2 control structures are examined and design guidelines are proposed for ramp compensations based on the factorized small-signal model. The analysis and design guideline are verified with simplis simulation and experimental results. / Master of Science

The future voltage regulator module (VRM) challenges of high bandwidth control with fast transient response, high current output, simple implementation, and efficient 48V solution are tackled in this dissertation. With the push for control bandwidth to meet design specifications for microprocessor VRM with larger and faster load transients, control can be saturated and lost for a significant period of time during transient. During this time, undesirable transient responses such as large undershoot and ringback occurs. Due to the loss of control, the existing tools to study the dynamic behavior of the system, such as small signal model, are insufficient to analyze the behavior of the system during this time. In order to have a better understanding of the system dynamic performance, the operation the VRM is analyzed in the state-plane for a clear visual understanding of the steady-state and transient behaviors. Using the state-plane, a simplified state-plane trajectory control is proposed for constant on-time (COT) control to achieve the best transient possible for applications with adaptive voltage positioning (AVP). When the COT control is lost during a load step-up transient, the state-plane trajectory control will extend on-time to provide the a near optimal transient response. By observing the COT control law in the state-plane, a simplified state-plane trajectory control with analog implementation is proposed to achieve the best transient possible with smooth transitions in and out of the steady-state COT control. The concept of the simplified state-plane trajectory control is then extended to multiphase COT. For multiphase operation, additional operating behavior, such as phase overlapping during transient and interleaving during steady-state, need to be taken into consideration to design the desired state-plane trajectory control. A simple state-plane trajectory control with improved Ton extension is proposed and verified using multiphase COT control. After tackling the state-plane trajectory control for current mode COT, the idea is then extended to V2 COT. V2 COT is a more advanced current mode control which requires a more advanced state-plane trajectory control to COT. By calculating the intersection of the extended on-stage trajectory during transient and the ideal off trajectory in the form of a current limiting wall, a near optimal transient response can be achieved. For V2 COT with state-plane trajectory control, implementations using inductor vs. capacitor current, effect of component tolerance, and effect of IC delay are studied. The proposed state-plane trajectory control is then extended to enhanced V2 COT. Aside from tackling existing VRM challenges, the future datacenter 48V VRM challenge of a high efficiency, high power density solution to meet the VRM specifications is studied. The sigma converter is proposed for the 48V VRM solution due to exhibition of high efficiency and high-power density from hardware evaluation. An accurate model for the sigma converter is derived using the new modeling approach of modularizing the small signal components. Using the proposed model, the sigma converter is shown to naturally have very low output impedance, making the sigma converter suitable for microprocessor applications. The sigma converter is designed and optimized to achieve AVP and very fast transient response using both voltage-mode and current-mode controls. / Doctor of Philosophy / Microprocessors, such as central processing unit (CPU) and graphics processing unit (GPU) are the basis of today's electronics. In the recent decades, the demand for more powerful and faster data processing lead to a significant increase in power consumption by these microprocessors. Even with the introduction of multi-core processors and adaptive voltage positioning (AVP) to reduce the average power provided by the power supplies, the microprocessor can still draw a large amount of instantaneous power in a short period of time. With the microprocessors demanding high amount of current at fast slew-rate, the challenges for the next generation of microprocessor power supply, or voltage regulator modules (VRM), are fast response speed to ensure proper operation of the microprocessors, and high efficiency VRM to minimize the overall system power consumption. The challenge of a VRM with fast response speed is tackled first. To meet the AVP and transient requirements of microprocessor, the VR need to utilize high-bandwidth control methods. Of the control methods used by the industry, high control bandwidth can be easily achieved using constant on-time (COT) control. With the ever-increasing output current level and transient slew-rate requirements, COT control can saturate and lose its steady-state control for a period of time during load step-up transient. During this time, the system will operate with a fixed frequency control until COT control is recovered. Although the method is widely used in the industry, the method is too slow to meet the transient requirements. Many state-of-art methods have been proposed to resolve the load step-up transient issue of COT. However, of the methods proposed, it is difficult to optimize the transient improvement while having a simple analog implementation to ensure a fast response for the wide operating range and aggressive transient conditions observed in microprocessor VRM application. In this dissertation, COT control is studied using the state-plane to provide a clear visual understanding of the transient behavior of the control. Using the state-plane, a state-plane trajectory control is proposed to achieve near optimal load step-up transient response. The concept is then extended to multiphase VRM, which is typically used for high current applications. The state-plane trajectory control concept is then further extended to V2 COT control for VRM without AVP, such as those used by GPU and smartphone CPU. For the proposed state-plane trajectory controls, hardware implementation, evaluation, and experimental results are provided. After tackling the challenge of a VRM with fast response speed, the challenge of an efficient VRM is then tackled. In recent years, a significant amount of research has been put into studying VRM for a power delivery architecture which uses a 48V bus instead of the 12V bus. By using the 48V bus, less redundancy in the power delivery path can greatly increase the overall system efficiency if the VRM stage retains its efficiency. However, the increase in input voltage for the VRM provides an additional challenge to maintain high efficiency for the VRM stage itself. To maintain good efficiency, it is difficult to increase converter switching frequency beyond 300kHz. This limitation on switching frequency will limit the ability to achieve high bandwidth design and fast transient requirements. A 48V VRM using a different topology, the sigma converter, has demonstrated high-efficiency and high-power density, but the converter behavior and control methodology for VRM application is unclear. In this dissertation, the modeling and control of the sigma converter are studied using the proposed small-signal model. By evaluating the proposed small-signal model, the sigma converter can naturally have very low output impedance, making it an ideal candidate for 48V VRM. Then, the design guideline of the sigma converter with current-mode control is provided. With the work discussed in this dissertation, further study of the sigma converter with COT and state-plane trajectory control can be conducted in the future.

Smart cameras operate mostly in sleep mode, which is light load for power supplies. Typical buck converter applications have low efficiency under the light load condition, primarily from their power stage and control being optimized for heavy load. The battery life of a smart camera can be extended through improvement of the light load efficiency of the buck converter. This thesis research investigated the first stage converter of a car black box to provide power to a microprocessor, camera, and several other peripherals. The input voltage of the converter is 12 V, and the output voltage is 5 V with the load range being 20 mA (100 mW) to 1000 mA (5000 mW). The primary design objective of the converter is to improve light load efficiency. A 3-level buck converter and its control scheme proposed by Reusch were adopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs and one more capacitor than a synchronous buck converter. Q1 and Q2 are considered the top MOSFETs, while Q3 and Q4 are the synchronous ones. The extra capacitor is used as a second power source to supply the load, which is connected between the source of Q1 and the drain of Q2 and the source of Q3 and the drain of Q4. The methods considered to improve light load efficiency are: PFM (pulse frequency modulation) control scheme with DCM (discontinuous conduction mode) and use of Schottky diodes in lieu of the synchronous MOSFETs, Q3 and Q4. The 3-level buck converter operates in CCM for heavy load above 330 mA and DCM for light load below 330 mA. The first method uses a COT (constant on-time) valley current mode controller that has a built in inductor current zero-crossing detector. COT is used to implement PFM, while the zero-crossing detector allows for DCM. The increase in efficiency comes from reducing the switching frequency as the load decreases by minimizing switching and gate driving loss. The second method uses an external current sense amplifier and a comparator to detect when to shut down the gate drivers for Q3 and Q4. Schottky diodes in parallel with Q3 and Q4 carry the load current when the MOSFETs are off. This increases the efficiency through a reduction in switching loss, gate driving loss, and gate driver power consumption. The proposed converter is prototyped using discrete components. LTC3833 is used as the COT valley current mode controller, which is the center of the control scheme. The efficiency of the 3-level buck converter was measured and ranges from 82% to 95% at 100 mW and 5000 mW, respectively. The transient response of the converter shows no overshoot due to a 500 mA load step up or down, and the output voltage ripple is 30 mV. The majority of the loss comes from the external components, which include a D FF (D flip-flop), AND gate, OR gate, current sense chip, comparator, and four gate drivers. The proposed converter was compared to two off-the-shelf synchronous buck converters. The proposed converter has good efficiency and performance when compared to the other converters, despite the fact that the converter is realized using discrete components. / Master of Science

<p>У докторској дисертацији&nbsp; приказани су резултати развијених и примењених коинцидентних метода за временску анализу нуклеарних процеса. Експериментални коинцидентни системи засновани су на&nbsp; HPGe&nbsp; и пластичним сцинтилационим детекторима.&nbsp; Извршена су три експеримента, која су показала примењивост развијених коинцидентних система. Први део експерименталног дела обухвата анализе временских варијација интензитета космичког зрачења посредством нискоенергијских фотона. Показано је да се праћењем интензитета нискоенергијских фотона у току времена у различитим енергијским регионима остварује бољи увид у анализу фонских догађаја, стварајући предуслове за извођење експеримената који трагају за ретким нуклеарним процесима. Поред праћења временских варијација интензитета, метода се може применити и&nbsp; на детекцију периодичних и апериодичних догађаја повезаних са активношћу Сунца. Други део дисертације обухватао је истраживања везана&nbsp; за&nbsp; детекцију потенцијалних&nbsp; флуктуација константе распада 22 Na. Развијен је коинцидентни систем&nbsp; и&nbsp; у току времена је&nbsp; праћен интензитет анихилационе линије, која је резултат анихилације позитрона емитованог распадом 22Na.&nbsp; За време трајања&nbsp; аквизиције података, нису пронађена значајна одступања испитиване константе распада од стандардног експоненцијалног закона радиоактивног распада. У трећем делу експерименталног рада, приказана је коинцидентна метода за временско раздвајање догађаја индукованих мионима и неутронима у околини детекторског система. Добијена је временска крива у експерименту и извршена је детаљна анализа различитих временских региона. Извршене су Монте Карло симулације, на основу којих је добијена временска крива. Анализом различитих региона симулиране временске криве, показано је да се ови догађаји могу раздвојити у две велике групе&ndash;брзе и споре догађаје. Међу спорим догађајима, показано је да се може направити разлика између догађаја индукованих мионима, међу којима доминира анихилација, и догађаја индукованих неутронима, који спадају у закаснеле догађаје у групи спорих догађаја. Добијено је да неутрони највише доприносе нискоенергијском региону, првенствено у региону до&nbsp; &asymp;50&nbsp; keV,&nbsp; што их чини&nbsp; нежељеном кариком фонских догађаја у експериментима који трагају за ретким нуклеарним догађајима. На основу резултата симулација, анализирани су електромагнетни и хадронски процеси индуковани мионима и неутронима, као и удели мионске и неутронске компоненте у коинцидентном спектру HPGe&nbsp; детектора и директном спектру пластичног сцинтилационог детектора. Закључено је да нискоенергијском спектру,&nbsp; који је превасходно значајан за ретке нуклеарне процесе,&nbsp; доминантно доприносе неутрони.</p> / <p>U doktorskoj disertaciji&nbsp; prikazani su rezultati razvijenih i primenjenih koincidentnih metoda za vremensku analizu nuklearnih procesa. Eksperimentalni koincidentni sistemi zasnovani su na&nbsp; HPGe&nbsp; i plastičnim scintilacionim detektorima.&nbsp; Izvršena su tri eksperimenta, koja su pokazala primenjivost razvijenih koincidentnih sistema. Prvi deo eksperimentalnog dela obuhvata analize vremenskih varijacija intenziteta kosmičkog zračenja posredstvom niskoenergijskih fotona. Pokazano je da se praćenjem intenziteta niskoenergijskih fotona u toku vremena u različitim energijskim regionima ostvaruje bolji uvid u analizu fonskih događaja, stvarajući preduslove za izvođenje eksperimenata koji tragaju za retkim nuklearnim procesima. Pored praćenja vremenskih varijacija intenziteta, metoda se može primeniti i&nbsp; na detekciju periodičnih i aperiodičnih događaja povezanih sa aktivnošću Sunca. Drugi deo disertacije obuhvatao je istraživanja vezana&nbsp; za&nbsp; detekciju potencijalnih&nbsp; fluktuacija konstante raspada 22 Na. Razvijen je koincidentni sistem&nbsp; i&nbsp; u toku vremena je&nbsp; praćen intenzitet anihilacione linije, koja je rezultat anihilacije pozitrona emitovanog raspadom 22Na.&nbsp; Za vreme trajanja&nbsp; akvizicije podataka, nisu pronađena značajna odstupanja ispitivane konstante raspada od standardnog eksponencijalnog zakona radioaktivnog raspada. U trećem delu eksperimentalnog rada, prikazana je koincidentna metoda za vremensko razdvajanje događaja indukovanih mionima i neutronima u okolini detektorskog sistema. Dobijena je vremenska kriva u eksperimentu i izvršena je detaljna analiza različitih vremenskih regiona. Izvršene su Monte Karlo simulacije, na osnovu kojih je dobijena vremenska kriva. Analizom različitih regiona simulirane vremenske krive, pokazano je da se ovi događaji mogu razdvojiti u dve velike grupe&ndash;brze i spore događaje. Među sporim događajima, pokazano je da se može napraviti razlika između događaja indukovanih mionima, među kojima dominira anihilacija, i događaja indukovanih neutronima, koji spadaju u zakasnele događaje u grupi sporih događaja. Dobijeno je da neutroni najviše doprinose niskoenergijskom regionu, prvenstveno u regionu do&nbsp; &asymp;50&nbsp; keV,&nbsp; što ih čini&nbsp; neželjenom karikom fonskih događaja u eksperimentima koji tragaju za retkim nuklearnim događajima. Na osnovu rezultata simulacija, analizirani su elektromagnetni i hadronski procesi indukovani mionima i neutronima, kao i udeli mionske i neutronske komponente u koincidentnom spektru HPGe&nbsp; detektora i direktnom spektru plastičnog scintilacionog detektora. Zaključeno je da niskoenergijskom spektru,&nbsp; koji je prevashodno značajan za retke nuklearne procese,&nbsp; dominantno doprinose neutroni.</p> / <p>In&nbsp; this&nbsp; doctoral&nbsp; thesis,&nbsp; the&nbsp; results&nbsp; of&nbsp; the&nbsp; developed and&nbsp; applied&nbsp; coincidence&nbsp;&nbsp; methods&nbsp; on&nbsp; the&nbsp; timeanalysis&nbsp; of&nbsp; nuclear&nbsp; processes&nbsp; are&nbsp; presented. Coincidence systems, used in presented experiments, are&nbsp; based&nbsp; on&nbsp; the&nbsp; HPGe&nbsp; and&nbsp; plastic&nbsp; scintillation detectors.&nbsp; Three&nbsp; experiments&nbsp; were&nbsp; performed,showing&nbsp; a&nbsp; wide&nbsp; application&nbsp; of&nbsp; the&nbsp; developed coincidence&nbsp; systems.&nbsp; The&nbsp; first&nbsp; part&nbsp; of&nbsp; the experimental work involves the analysis of the time&nbsp; variations of cosmic rays via low-energy photons. It was&nbsp; shown&nbsp; that&nbsp; by&nbsp; analyzing&nbsp; the&nbsp; intensity&nbsp; of&nbsp; lowenergy photons better insight into the behavior of thebackground&nbsp; events&nbsp; is&nbsp; provided,&nbsp; which&nbsp; is&nbsp;&nbsp; especially important&nbsp; as&nbsp; a&nbsp; precondition&nbsp; for&nbsp; rare&nbsp; nuclear&nbsp; events experiments.&nbsp; Furthermore,&nbsp; it&nbsp; was&nbsp; shown&nbsp; that&nbsp; this method can be applied in order to search for periodic or aperiodic events resulting from the Sun activity. The&nbsp; second&nbsp; part&nbsp; contains&nbsp; the&nbsp; research&nbsp; of&nbsp; the&nbsp; 22Na decay constant fluctuations. The coincidence system was&nbsp; developed&nbsp; and&nbsp; the&nbsp; intensity&nbsp; of&nbsp; the&nbsp; annihilation line,&nbsp; resulting&nbsp; from&nbsp; annihilation&nbsp; of&nbsp; the&nbsp; positrons emitted from 22Na, was followed with time. During&nbsp; he&nbsp; acquisition&nbsp; time,&nbsp; no&nbsp; significant&nbsp; deviations&nbsp; from the standard exponential radioactive decay law were found. In&nbsp; the&nbsp; third&nbsp; part&nbsp; of&nbsp; the&nbsp; experimental&nbsp; work,&nbsp; the coincidence&nbsp; method&nbsp; for&nbsp; time&nbsp; separation&nbsp; of&nbsp; the events,&nbsp; induced&nbsp; by&nbsp; cosmic&nbsp; muons&nbsp; and&nbsp; neutrons&nbsp; in the&nbsp; vicinity&nbsp; of&nbsp; the&nbsp; detectors&nbsp; system,&nbsp; was&nbsp; presented. The time curve was obtained in the experiment and the&nbsp; detailed&nbsp; analysis&nbsp; of&nbsp; the&nbsp; different&nbsp; time&nbsp; regions was&nbsp; performed.&nbsp; The&nbsp; Monte&nbsp; Carlo&nbsp; simulations&nbsp; were conducted&nbsp; and&nbsp; the&nbsp; time&nbsp; curve&nbsp; from&nbsp; the&nbsp; simulation results was obtained. Analyzing the different regions of the simulated time curve, it was noticed that these events can be separated into two groups&ndash;prompt and delayed.&nbsp; Between&nbsp; delayed&nbsp; events,&nbsp; it&nbsp; was&nbsp; concluded that&nbsp; events&nbsp; induced&nbsp; by&nbsp; muons,&nbsp; dominantly annihilation&nbsp; line,&nbsp; and&nbsp; events&nbsp; induced&nbsp; by&nbsp; neutrons, which&nbsp; may&nbsp; be&nbsp; classified&nbsp; as&nbsp; more&nbsp; delayed&nbsp; events&nbsp; in the&nbsp; group&nbsp; of&nbsp; the&nbsp; delayed&nbsp; events,&nbsp; can&nbsp; be distinguished.&nbsp; It&nbsp; was&nbsp; concluded&nbsp; the&nbsp; neutrons dominantly&nbsp; contribute&nbsp; to&nbsp; the&nbsp; low-energy&nbsp; region, mostly&nbsp; in&nbsp; the&nbsp; region&nbsp; to&nbsp; &asymp;50&nbsp; keV,&nbsp; which&nbsp; makes neutrons&nbsp; an&nbsp; important&nbsp; background&nbsp; in&nbsp; the experiments searching for rare nuclear events. Based on&nbsp; the&nbsp; simulation&nbsp; results,&nbsp; electromagnetic&nbsp; and hadronic processes induced by muons and neutrons, as&nbsp; well&nbsp; as&nbsp; portions&nbsp; of&nbsp; muon&rsquo;s&nbsp; and&nbsp; neutron&rsquo;s component&nbsp; in&nbsp; the&nbsp; coincidence&nbsp; spectrum&nbsp; of&nbsp; HPGe detector&nbsp; and&nbsp; direct&nbsp; spectrum&nbsp; of&nbsp; the&nbsp; plastic scintillation&nbsp; detector&nbsp; were&nbsp; analyzed.&nbsp; It&nbsp; was concluded&nbsp; that&nbsp; in&nbsp; the&nbsp; low-energy&nbsp; part&nbsp; of&nbsp; the spectrum,&nbsp; primarily important for the search for rare nuclear&nbsp; events,&nbsp; dominant&nbsp; influence&nbsp; is&nbsp; originated from cosmic neutrons.</p>