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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
41

Developing Box-Pushing Behaviours Using Evolutionary Robotics

Van Lierde, Boris January 2011 (has links)
The context of this report and the IRIDIA laboratory are described in the preface. Evolutionary Robotics and the box-pushing task are presented in the introduction.The building of a test system supporting Evolutionary Robotics experiments is then detailed. This system is made of a robot simulator and a Genetic Algorithm. It is used to explore the possibility of evolving box-pushing behaviours. The bootstrapping problem is explained, and a novel approach for dealing with it is proposed, with results presented.Finally, ideas for extending this approach are presented in the conclusion.
42

Essays in Industrial Organization and Econometrics

Blevins, Jason Ryan January 2010 (has links)
<p>This dissertation consists of three chapters relating to</p> <p>identification and inference in dynamic microeconometric models</p> <p>including dynamic discrete games with many players, dynamic games with</p> <p>discrete and continuous choices, and semiparametric binary choice and</p> <p>duration panel data models.</p> <p>The first chapter provides a framework for estimating large-scale</p> <p>dynamic discrete choice models (both single- and multi-agent models)</p> <p>in continuous time. The advantage of working in continuous time is</p> <p>that state changes occur sequentially, rather than simultaneously,</p> <p>avoiding a substantial curse of dimensionality that arises in</p> <p>multi-agent settings. Eliminating this computational bottleneck is</p> <p>the key to providing a seamless link between estimating the model and</p> <p>performing post-estimation counterfactuals. While recently developed</p> <p>two-step estimation techniques have made it possible to estimate</p> <p>large-scale problems, solving for equilibria remains computationally</p> <p>challenging. In many cases, the models that applied researchers</p> <p>estimate do not match the models that are then used to perform</p> <p>counterfactuals. By modeling decisions in continuous time, we are able</p> <p>to take advantage of the recent advances in estimation while</p> <p>preserving a tight link between estimation and policy experiments. We</p> <p>also consider estimation in situations with imperfectly sampled data,</p> <p>such as when we do not observe the decision not to move, or when data</p> <p>is aggregated over time, such as when only discrete-time data are</p> <p>available at regularly spaced intervals. We illustrate the power of</p> <p>our framework using several large-scale Monte Carlo experiments.</p> <p>The second chapter considers semiparametric panel data binary choice</p> <p>and duration models with fixed effects. Such models are point</p> <p>identified when at least one regressor has full support on the real</p> <p>line. It is common in practice, however, to have only discrete or</p> <p>continuous, but possibly bounded, regressors. We focus on</p> <p>identification, estimation, and inference for the identified set in</p> <p>such cases, when the parameters of interest may only be partially</p> <p>identified. We develop a set of general results for</p> <p>criterion-function-based estimation and inference in partially</p> <p>identified models which can be applied to both regular and irregular</p> <p>models. We apply our general results first to a fixed effects binary</p> <p>choice panel data model where we obtain a sharp characterization of</p> <p>the identified set and propose a consistent set estimator,</p> <p>establishing its rate of convergence under different conditions.</p> <p>Rates arbitrarily close to <italic>n<super>-1/3</super></italic> are</p> <p>possible when a continuous, but possibly bounded, regressor is</p> <p>present. When all regressors are discrete the estimates converge</p> <p>arbitrarily fast to the identified set. We also propose a</p> <p>subsampling-based procedure for constructing confidence regions in the</p> <p>models we consider. Finally, we carry out a series of Monte Carlo</p> <p>experiments to illustrate and evaluate the proposed procedures. We</p> <p>also consider extensions to other fixed effects panel data models such</p> <p>as binary choice models with lagged dependent variables and duration</p> <p>models.</p> <p>The third chapter considers nonparametric identification of dynamic</p> <p>games of incomplete information in which players make both discrete</p> <p>and continuous choices. Such models are commonly used in applied work</p> <p>in industrial organization where, for example, firms make discrete</p> <p>entry and exit decisions followed by continuous investment decisions.</p> <p>We first review existing identification results for single agent</p> <p>dynamic discrete choice models before turning to single-agent models</p> <p>with an additional continuous choice variable and finally to</p> <p>multi-agent models with both discrete and continuous choices. We</p> <p>provide conditions for nonparametric identification of the utility</p> <p>function in both cases.</p> / Dissertation
43

Low-Power Continuous-Time Sigma-Delta Modulator for GSM

Liu, Jun-hong 12 July 2012 (has links)
Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator. The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design. The proposed sigma-delta modulator used TSMC 0.18£gm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW. Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.
44

Essays on the Predictability and Volatility of Asset Returns

Jacewitz, Stefan A. 2009 August 1900 (has links)
This dissertation collects two papers regarding the econometric and economic theory and testing of the predictability of asset returns. It is widely accepted that stock returns are not only predictable but highly so. This belief is due to an abundance of existing empirical literature fi nding often overwhelming evidence in favor of predictability. The common regressors used to test predictability (e.g., the dividend-price ratio for stock returns) are very persistent and their innovations are highly correlated with returns. Persistence when combined with a correlation between innovations in the regressor and asset returns can cause substantial over-rejection of a true null hypothesis. This result is both well documented and well known. On the other hand, stochastic volatility is both broadly accepted as a part of return time series and largely ignored by the existing econometric literature on the predictability of returns. The severe e ffect that stochastic volatility can have on standard tests are demonstrated here. These deleterious e ffects render standard tests invalid. However, this problem can be easily corrected using a simple change of chronometer. When a return time series is read in the usual way, at regular intervals of time (e.g., daily observations), then the distribution of returns is highly non-normal and displays marked time heterogeneity. If the return time series is, instead, read according to a clock based on regular intervals of volatility, then returns will be independent and identically normally distributed. This powerful result is utilized in a unique way in each chapter of this dissertation. This time-deformation technique is combined with the Cauchy t-test and the newly introduced martingale estimation technique. This dissertation nds no evidence of predictability in stock returns. Moreover, using martingale estimation, the cause of the Forward Premium Anomaly may be more easily discerned.
45

Calibrated Continuous-Time Sigma-Delta Modulators

Lu, Cho-Ying 2010 May 1900 (has links)
To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.
46

A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters

Sundar, Arun 2011 December 1900 (has links)
The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.
47

Decision Making for Information Security Investments

Yeo, M. Lisa Unknown Date
No description available.
48

Eye opening monitor for optimized self-adaptation of low-power equalizers in multi-gigabit serial links

Narayanan, Anand January 2013 (has links)
In modern day communication systems, there is a constant demand for increase in transmission rates. This is however limited by the bandwidth limitation of the channel. Inter symbol interference (ISI) imposes a great threat to increasing data rates by degrading the signal quality. Equalizers are used at the receiver to compensate for the losses in the channel and thereby greatly mitigate ISI. Further, an adaptive equalizer is desired which can be used over a channel whose response is unknown or is time-varying. A low power equalizing solution in a moderately attenuated channel is an analog peaking filter which boosts the signal high frequency components. Such conventional continuous time linear equalizers (CTLE) provide a single degree of controllability over the high frequency boost. A more complex CTLE has been designed which has two degrees of freedom by controlling the high frequency boost as well as the range of frequencies over which the boost is applied. This extra degree of controllability over the equalizer response is desired to better adapt to the varying channel response and result in an equalized signal with a wider eye opening. A robust adaptation technique is necessary to tune the equalizer characteristics. Some of the commonly used techniques for adaptation of CTLEs are based on energy comparison criterion in the frequency domain. But the adaptation achieved using these techniques might not be optimal especially for an equalizer with two degrees of controllability. In such cases an eye opening monitor (EOM) could be used which evaluates the actual signal quality in time domain. The EOM gives an estimate on the signal quality by measuring the eye opening of the equalized signal in horizontal and vertical domain. In this thesis work a CTLE with two degrees of freedom with an EOM based adaptation system has been implemented.
49

Tunable, linear, G<subscript m>-C filters /

Wang, Yanjie, January 1900 (has links)
Thesis (M. App. Sc.)--Carleton University, 2002. / Includes bibliographical references (p. 103-106). Also available in electronic format on the Internet.
50

Improved design techniques for analog and mixed circuits /

Nishida, Yoshio. January 1900 (has links)
Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 79-82). Also available on the World Wide Web.

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