Η παρούσα ειδική ερευνητική εργασία εκπονήθηκε στα πλαίσια του Διατμηματικού Προγράμματος Μεταπτυχιακών Σπουδών Ειδίκευσης στην “Ηλεκτρονική και Επεξεργασία της Πληροφορίας” στο Τμήμα Φυσικής του Πανεπιστημίου Πατρών. Αντικείμενο της παρούσας εργασίας είναι η σχεδίαση και ανάπτυξη ενός βασικού μικροϋπολογιστικού συστήματος με τη χρήση της VHDL και FPGAs. Το σύστημα βασίζεται σε μία επαυξημένη, σε δυνατότητες, εκδοχή της σχετικά απλής cpu του Carpinelli και ενσωματώνει τη δυνατότητα παράλληλης διασύνδεσης μίας σειράς περιφερειακών διατάξεων και υποκυκλωμάτων. Στο πρώτο κεφάλαιο παρουσιάζεται πλήρως η σχεδίαση ενός τέτοιου συστήματος και μελετάται η δομή των επιμέρους δομικών στοιχείων που το απαρτίζουν. Στο δεύτερο κεφάλαιο παρουσιάζεται η περιγραφή του μικροϋπολογιστικού συστήματος σε γλώσσα VHDL και η πλήρης εξομοίωσή του με τη βοήθεια του λογισμικού Quartus v7.2 της ALTERA. Στο τελευταίο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροϋπολογιστικού συστήματος στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA. / This project objective is the design and development of an FPGA based microcomputer system in VHDL. The system is based on an enhanced version of Carpinelli’s relative simple cpu and is implemented with parallel input and output ports and interrupts. The first chapter presents the full design of such a system and study the structure of the individual components that compose it. The second chapter presents the implementation of the microcomputer system in VHDL and the simulation results using Quartus v7.2 software suite. The last chapter presents the implementation of the system in a FPGA using DE2 development board of ALTERA.

A radio base station (RBS) may become overloaded if too many mobile devices communicate with it at the same time. This could happen at for instance sport events or in the case of accidents. To prevent CPU overload, the RBS is provided with a controller that adjusts the acceptance rate, the maximum number of connection requests that can be accepted per time interval. The current controller is tuned in real radio base stations and the procedure is both time consuming and expensive. This, combined with the fact that the mobile data usage is predicted to increase puts more pressure on today's system. Thus, there is a need to be able to simulate the system in order to suggest an alternative controller. In this thesis, an implementation of the system is developed in Matlab in order to simulate the RBS system load control behaviour. A CPU load model is estimated using system identification. The current version of the CPU load controller and an alternative PI CPU load controller are implemented. Both are evaluated on different test cases and this shows that it is possible to increase the performance of the system with the alternative CPU load controller, both in terms of lower amount of rejected connection requests and decreased CPU load overshoot.

[pt] O objetivo deste trabalho é estudar a integração de mecanismos de reserva de recursos computacionais em infra-estruturas de software para aglomerados de computadores. Para realizar esse estudo, foi utilizado o framework CSBase, que é uma infra-estrutura de software concebida com o intuito de dar apoio à implementação e integração de aplicações científicas em ambientes distribuídos e heterogêneos. O CSBase oferece suporte à execução de aplicações em ambientes distribuídos e ao gerenciamento de usuários e de recursos computacionais, tais como computadores, arquivos de dados e aplicações. Entretanto, as primeiras aplicações desenvolvidas com o CSBase já demonstraram que são necessários mecanismos que permitam um melhor gerenciamento e controle dos recursos computacionais disponíveis em ambientes distribuídos, e especialmente em aglomerados de computadores dedicados à execução de aplicações de alto desempenho. Neste trabalho, apresentamos uma extensão ao framework CSBase que possibilita a reserva de processador para aplicações de usuários do sistema, e assim permitindo um gerenciamento mais eficiente dos recursos computacionais disponíveis. Essa extensão também garante que serão efetuadas as adaptações necessárias para acomodar eventuais variações no perfil de uso do processador por parte das aplicações. Como resultado dessa extensão, obteve-se a integração entre a monitoração de recursos distribuídos, a iniciação remota de aplicações, e um mecanismo de reserva de processador que proporcionou uma melhor utilização das máquinas disponíveis. / [en] The goal of this work is to study the integration of resource reservation mechanisms with software infrastructures for cluster computing. To perform this study, we used the CSBase framework, which is a software infrastructure conceived to support the implementation and integration of scientific applications in heterogeneous and distributed environments. CSBase offers support for application execution in distributed environments, as well as support for management of users and computational resources, such as computers, data files and applications. However, the first applications developed with CSBase showed that it requires mechanisms to allow a better management of resources available in distributed environments, and especially in clusters of computers dedicated to execute high performance applications. In this work, we present an extension to CSBase that provides the reservation of processor time to user applications, thus allowing a more efficient resource management. This extension also guarantees that all required adaptations will be performed to accommodate variations in the applications´ processor usage profile. As a result of this extension, we achieved the integration of mechanisms for distributed resource monitoring, remote application execution, and processor reservation, providing a better utilization among the available machines.

With the development of modern smartphones, mobile devices have become ubiquitous in our daily lives. With high processing capabilities and a vast number of applications, users now need them for both business and personal tasks. Unfortunately, battery technology did not scale with the same speed as computational power. Hence, modern smartphone batteries often last for less than a day before they need to be recharged. One of the most power hungry components is the central processing unit (CPU). Multiple techniques are applied to reduce CPU energy consumption. Among them is dynamic voltage and frequency scaling (DVFS). This technique reduces energy consumption by dynamically changing CPU supply voltage depending on the currently running workload. Reducing voltage, however, also makes it necessary to reduce the clock frequency, which can have a significant impact on task performance. Current DVFS algorithms deliver a good user experience, however, as experiments conducted later in this thesis will show, they do not deliver an optimal energy efficiency for an interactive mobile workload. This thesis presents methods and tools to determine where energy can be saved during mobile workload execution when using DVFS. Furthermore, an improved DVFS technique is developed that achieves a higher energy efficiency than the current standard. One important question when developing a DVFS technique is: How much can you slow down a task to save energy before the negative effect on performance becomes intolerable? The ultimate goal when optimising a mobile system is to provide a high quality of experience (QOE) to the end user. In that context, task slowdowns become intolerable when they have a perceptible effect on QOE. Experiments conducted in this thesis answer this question by identifying workload periods in which performance changes are directly perceptible by the end user and periods where they are imperceptible, namely interaction lags and interaction idle periods. Interaction lags are the time it takes the system to process a user interaction and display a corresponding response. Idle periods are the periods between interactions where the user perceives the system as idle and ready for the next input. By knowing where those periods are and how they are affected by frequency changes, a more energy efficient DVFS governor can be developed. This thesis begins by introducing a methodology that measures the duration of interaction lags as perceived by the user. It uses them as an indicator to benchmark the quality of experience for a workload execution. A representative benchmark workload is generated comprising 190 minutes of interactions collected from real users. In conjunction with this QOE benchmark, a DVFS Oracle study is conducted. It is able to find a frequency profile for an interactive mobile workload which has the maximum energy savings achievable without a perceptible performance impact on the user. The developed Oracle performance profile achieves a QOE which is indistinguishable from always running on the fastest frequency while needing 45% less energy. Furthermore, this Oracle is used as a baseline to evaluate how well current mobile frequency governors are performing. It shows that none of these governors perform particularly well and up to 32% energy savings are possible. Equipped with a benchmark and an optimisation baseline, a user perception aware DVFS technique is developed in the second part of this thesis. Initially, a runtime heuristic is introduced which is able to detect interaction lags as the user would perceive them. Using this heuristic, a reinforcement learning driven governor is developed which is able to learn good frequency settings for interaction lag and idle periods based on sample observations. It consumes up to 22% less energy than current standard governors on mobile devices, and maintains a low impact on QOE.

REGO, Paulo Antonio Leal. FairCPU: Uma arquitetura para provisionamento de máquinas virtuais utilizando características de processamento. 2012. 81 f. Dissertação (Mestrado em ciência da computação)- Universidade Federal do Ceará, Fortaleza-CE, 2012. / Submitted by Elineudson Ribeiro (elineudsonr@gmail.com) on 2016-07-12T15:06:42Z No. of bitstreams: 1 2012_dis_palrego.pdf: 5402392 bytes, checksum: 6ce44a55f28b19b0d7b237d0bd43f4cd (MD5) / Approved for entry into archive by Rocilda Sales (rocilda@ufc.br) on 2016-07-20T13:50:46Z (GMT) No. of bitstreams: 1 2012_dis_palrego.pdf: 5402392 bytes, checksum: 6ce44a55f28b19b0d7b237d0bd43f4cd (MD5) / Made available in DSpace on 2016-07-20T13:50:46Z (GMT). No. of bitstreams: 1 2012_dis_palrego.pdf: 5402392 bytes, checksum: 6ce44a55f28b19b0d7b237d0bd43f4cd (MD5) Previous issue date: 2012 / Resource scheduling is a key process for cloud computing platform, which generally uses virtual machines (VMs) as scheduling units. The use of virtualization techniques provides great flexibility with the ability to instantiate multiple VMs on one physical machine (PM), migrate them between the PMs and dynamically scale VM’s resources. The techniques of consolidation and dynamic allocation of VMs have addressed the impact of its use as an independent measure of location. It is generally accepted that the performance of a VM will be the same regardless of which PM it is allocated. This assumption is reasonable for a homogeneous environment where the PMs are identical and the VMs are running the same operating system and applications. Nevertheless, in a cloud computing environment, we expect that a set of heterogeneous resources will be shared, where PMs will face changes both in terms of their resource capacities and as also in data affinities. The main objective of this work is to propose an architecture to standardize the representation of the processing power by using processing units (PUs). Adding to that, the limitation of CPU usage is used to provide performance isolation and maintain the VM’s processing power at the same level regardless the underlying PM. The proposed solution considers the PMs heterogeneity present in the cloud infrastructure and provides scheduling policies based on PUs. The proposed architecture is called FairCPU and was implemented to work with KVM and Xen hypervisors. As study case, it was incorporated into a private cloud, built with the middleware OpenNebula, where several experiments were conducted. The results prove the efficiency of FairCPU architecture to use PUs to reduce VMs’ performance variability, as well as to provide a new way to represent and manage the processing power of the infrastructure’s physical and virtual machines. / O escalonamento de recursos é um processo chave para a plataforma de Computação em Nuvem, que geralmente utiliza máquinas virtuais (MVs) como unidades de escalonamento. O uso de técnicas de virtualização fornece grande flexibilidade com a habilidade de instanciar várias MVs em uma mesma máquina física (MF), modificar a capacidade das MVs e migrá-las entre as MFs. As técnicas de consolidação e alocação dinâmica de MVs têm tratado o impacto da sua utilização como uma medida independente de localização. É geralmente aceito que o desempenho de uma MV será o mesmo, independentemente da MF em que ela é alocada. Esta é uma suposição razoável para um ambiente homogêneo, onde as MFs são idênticas e as MVs estão executando o mesmo sistema operacional e aplicativos. No entanto, em um ambiente de Computação em Nuvem, espera-se compartilhar um conjunto composto por recursos heterogêneos, onde as MFs podem variar em termos de capacidades de seus recursos e afinidades de dados. O objetivo principal deste trabalho é apresentar uma arquitetura que possibilite a padronização da representação do poder de processamento das MFs e MVs, em função de Unidades de Processamento (UPs), apoiando-se na limitação do uso da CPU para prover isolamento de desempenho e manter a capacidade de processamento das MVs independente da MF subjacente. Este trabalho busca suprir a necessidade de uma solução que considere a heterogeneidade das MFs presentes na infraestrutura da Nuvem e apresenta políticas de escalonamento baseadas na utilização das UPs. A arquitetura proposta, chamada FairCPU, foi implementada para trabalhar com os hipervisores KVM e Xen, e foi incorporada a uma nuvem privada, construída com o middleware OpenNebula, onde diversos experimentos foram realizados para avaliar a solução proposta. Os resultados comprovam a eficiência da arquitetura FairCPU em utilizar as UPs para reduzir a variabilidade no desempenho das MVs, bem como para prover uma nova maneira de representar e gerenciar o poder de processamento das MVs e MFs da infraestrutura.

Submitted by Oliveira Flávia (flavia@sisbin.ufop.br) on 2014-01-27T18:38:17Z No. of bitstreams: 2 license_rdf: 23748 bytes, checksum: b92763cfc0af52c7c868455edfaf3266 (MD5) DISSERTAÇÃO_TerraMEObserverPipeline.pdf: 3329082 bytes, checksum: 03b5d8ae577625e3907998bfddef5119 (MD5) / Approved for entry into archive by Gracilene Carvalho (gracilene@sisbin.ufop.br) on 2014-02-03T12:05:31Z (GMT) No. of bitstreams: 2 license_rdf: 23748 bytes, checksum: b92763cfc0af52c7c868455edfaf3266 (MD5) DISSERTAÇÃO_TerraMEObserverPipeline.pdf: 3329082 bytes, checksum: 03b5d8ae577625e3907998bfddef5119 (MD5) / Made available in DSpace on 2014-02-03T12:05:31Z (GMT). No. of bitstreams: 2 license_rdf: 23748 bytes, checksum: b92763cfc0af52c7c868455edfaf3266 (MD5) DISSERTAÇÃO_TerraMEObserverPipeline.pdf: 3329082 bytes, checksum: 03b5d8ae577625e3907998bfddef5119 (MD5) Previous issue date: 2013 / A visualização científica é uma eficiente ferramenta de síntese, pois permite transformar o grande volume de dados científicos produzidos diariamente em informações relevantes. Quando aplicada em áreas como a de modelagem ambiental, ela contribui em diversos níveis, como, no desenvolvimento e melhoria dos modelos ambientais, interpretação e comunicação de resultados e no apoio à tomada de decisão e à definição de políticas públicas. A visualização é o resultado de uma sequência de processos de transformações, chamada pipeline, na qual imagens bidimensionais são construídas a partir dos dados em estudo. Apesar das arquiteturas de pipelines de visualização terem sido alvo de melhoria em diversas pesquisas recentes e serem aplicadas com sucesso na visualização de volumes massivos de dados, não foram encontrados relatos de plataformas de modelagem ambiental que utilizassem o conceito de pipeline em seus serviços de visualização. Por estas razões, este trabalho apresenta a concepção e o projeto de uma arquitetura de alto desempenho para pipelines destinados à visualização de simulações ambientais. Essa arquitetura chamada TerraME Observer foi implementada como uma extensão do simulador ambiental TerraME e avaliada segundo análise de desempenho e planejamento de capacidade. De forma cíclica e incremental, esses experimentos permitiram gradativamente identificar e reduzir gargalos de processamento. Comparando-se os desempenhos das versões inicial e final da arquitetura, os resultados dos experimentos mostram uma redução de 60% a 80% no tempo de resposta do serviço de visualização e um aumento inferior a 7% no consumo de memória. A arquitetura TerraME Observer é extensível, flexível e pode ser utilizada por qualquer outro ambiente de modelagem para implementar seus serviços de visualização. ___________________________________________________________________________ / ABSTRACT: Scientific Visualization is an efficient synthesis tool as it allows the transformation of a large volume of scientific data produced on a daily basis. When applied in areas such as environmental modeling, scientific visualization contributes on many levels, for example, in the development and improvement of environmental models, interpretation and communication of results, and support for decision-making and public policies. Visualization is the result of a sequence of transformations, called pipeline, in which two-dimensional images are constructed from the data in the study. Although the architectures of visualization pipelines have been targeted for improvement in several recent studies and been applied successfully in the visualization of massive volumes of data, there were no reports of environmental modeling platforms that used the concept of pipeline in their visualization services. For these reasons, this work presents the conception and design of an architecture for high-performance pipelines intended for viewing environmental simulations. This architecture, called TerraME Observer, was implemented as an extension of the simulator TerraME and evaluated through experiments for performance analysis and capacity planning. These experiments allowed a gradual and cyclical identification and reduction of processing bottlenecks. Comparing the performance of the initial and final versions of the architecture, the results of the experiments show a reduction in response time of visualization service with an improvement of between 60 to 80 per cent, and an increase of less than 7 per cent in memory consumption. The TerraME Observer architecture is extensible, flexible and can be used by any modeling environment to implement its visualization services.

In the latest years, the public’s interest in blockchain technology has been growing since it was brought up in 2008, primarily because of its ability to create an immutable ledger, for storing information that never will or can be changed. As an expanding chain structure, the act of nodes adding blocks to the chain is called mining which is regulated by consensus mechanism. In the most widely used consensus mechanism Proof of work, this process is based on computationally heavy guessing of hashes of blocks. Today, there are several prominent ways developed of performing this guessing, thanks to the development of hardware technology, either using the regular all-rounded computer processing unit (CPU), or using the more specialized graphics processing unit (GPU), or using dedicated hardware. This thesis studied the working principles of blockchain, implemented the crucial hash function used in Proof of Work consensus mechanism and other blockchain structures with the popular programming language Java on various platforms. CPU implementation is done with Java’s built-in functions and for GPU I used OpenCL ’ s Java binding JOCL. This project gives a quantified measurement for hash rate on different devices, determines that all the GPUs tested advantage over CPUs in performance and memory consumption. Java’s built-in function is easier to use but both of the implementations are doing well in platform independent that the same code can easily be executed on different platforms. Furthermore, based on the measurements, I did in-depth exploration of the principles and proposed future work, analyzed their application values combined with future possibilities of blockchain based on implementation difficulties and performance.

Vizz3D is a powerful 3D visualization system. The current version is neither perfect nor up-to-date. Furthermore, some important features are missing. In order to keep the tool valuable it needs to be maintained. I implemented a new feature allowing to save and load the view port in the graph to control the camera position. I also improved the CPU utilization and the navigation system to solve the limitations in Vizz3D and to improve the overall performance.

This thesis is an exploration of how a laptop system performance is affected by workload on the processor. The workload is represented by a process thread that is time consuming for the CPU and keeps the CPU continuously occupied with jobs. The load can be increased by adding more loading threads. The changes in the performance is measured by, for example, the processor utilisation, response time, priorities and temperature. The processor’s utilisation is affecting the system performance by how the processor is organising and distributing tasks. Increased workload require system methods that correspond to the load in order to maintain a certain system standard. Measuring the assigned thread priority numbers gives a more specific indication of which techniques the scheduler is using to handle the tasks. The response time characterises the impact of the workload relative time. It is investigated by timing the response of a system call, during an increasing workload of threads. The results illustrate an increasing growth of the response time, where a relative small added workload makes the system call about impractical to carry through at a particular load limit. The processor’s temperature and energy consumption entail changes in the system performance mainly in terms of the quality of the component, operationally and materially. It has also long-term effects on the surrounding components of the processor and on environmental issues. / Det här examensarbetet är en utforskning av hur en laptops prestanda påverkas under arbetsbelastning på processorn. Arbetsbelastningen utgörs av en processtråd som är tidskrävande för CPU:n och som håller CPU:n fullt sysselsatt med kontinuerligt arbete. Belastningen kan ökas genom att öka antalet processtrådar. Förändringar i systemets prestanda mäts bland annat utifrån processorns användningsgrad, responstid, prioriteringar och arbetstemperatur. Användningsgraden påverkar prestandan genom hur processorn får organisera sin arbetsfördelning. Ökad belastning erfordrar arbetsmetoder som möter belastningen för att kunna upprätthålla systemstandarden. Mätning av prioritetsnumrering ger en mer ingående bild av vilka tekniker som schemaläggaren kan använda vid den hanteringen. Responstiden ger ett mått på belastningens konsekvenser för operativsystemets prestation i förhållande till tidsåtgången. Den undersöks genom att mäta tiden för ett systemanrop vid allt tyngre belastningar. I resultatet framgår ett grafiskt samband där en relativt liten ökad belastning gör att anropet i praktiken blir ogenomförbart vid en viss belastningsgräns. Processorns energiförbrukning och arbetstemperatur medför förändringar i prestandan främst i form av kvaliteten på komponenten, arbetsmässigt och materiellt. Det har även mer långsiktiga effekter på omgivande komponenter och ur miljösynpunkt.

At the moment, two main web platforms have the monopoly of web service business; NET and J2EE have been competitors in this area for many years. Within last years, a technological advance has occurred with the appearance of Mono, an open source project that allows NET technologies to be taken into operating systems other than Microsoft Windows. This opens an information gap that needs to be solved with a new and actualised performance analysis. This thesis work identifies the performance characteristics of the web platforms on heterogeneous systems. The aim of this study is to investigate different performance characteristics of .NET and J2EE web services in heterogeneous systems. The student systems are Windows 7 and Ubuntu Linux. A set of web services is built following different service structures, which are then exposed to some quantitative and qualitative test following predefined criteria. The results demonstrate that both .NET and J2EE are suitable web platforms under different circumstances, based mostly on the communication protocol and operating system. This work identifies the best combination of web platform and operating system for each of the web service structures, which can vary for each company.