<p>Timing-related defects are becoming increasingly important in nanometer-technology integrated circuits (ICs). Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. All these effects are noticeable in today's technologies and they are likely to become more prominent in the next-generation process technologies~\cite{itrs2007}.</p><p>The detection of small-delay defects (SDDs) is difficult because of the small size of the introduced delay. Although the delay introduced by each SDD is small, the overall impact can be significant if the target path is critical, has low slack, or includes many SDDs. The overall delay of the path may become larger than the clock period, causing circuit failure or temporarily incorrect results. As a result, the detection of SDDs typically requires fault excitation through least-slack paths. However, widely-used automatic test-pattern generation (ATPG) techniques are not effective at exciting small delay defects. On the other hand, the usage of commercially available timing-aware tools is expensive in terms of pattern count inflation and very high test-generation times. Furthermore, these tools do not target real physical defects.</p><p>SDDs are induced not only by physical defects, but also by run-time variations such as crosstalk and power-supply noise. These variations are ignored by today's commercial ATPG tools. As a result, new methods are required for comprehensive coverage of SDDs.</p><p>Test data volume and test application time are also major concerns for large industrial circuits. In recent years, many compression techniques have been proposed and evaluated using industrial designs. However, these methods do not target sequence- or timing-dependent failures while compressing the test patterns. Since timing-related failures in high-performance integrated circuits are now increasingly dominated by SDDs, it is necessary to develop timing-aware compression techniques.</p><p>This thesis addresses the problem of selecting the most effective test patterns for detecting SDDs. A new gate and interconnect delay-defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from a large pattern set generated using timing-unaware ATPG. It offers significantly lower computational complexity and it excites a larger number of long paths compared to previously proposed timing-aware ATPG methods. It is shown that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, process variations, and crosstalk. The proposed technique also serves as the basis for an efficient SDD-aware test compression scheme. The effectiveness of the proposed technique is highlighted for industrial circuits.</p><p>In summary, this research is targeted at the testing of SDDs caused by various underlying reasons. The proposed techniques are expected to generate high-quality and compact test patterns for various types of defects in nanometer ICs. The results of this research are expected to provide low-cost and effective test methods for nanometer devices, and they will lead to higher shipped-product quality.</p> / Dissertation

True time delay networks are one of the most critical structures of wideband phased-array antenna systems which are frequently used in self-protection and electronic warfare applications. In order to direct the main beam of a wideband phased-array antenna to the desired direction / phase values, which are linearly dependent to frequency, are essential. Due to the phase characteristics of the true-time delay networks, beam squint problems for broadband phased array systems are minimized. In this thesis, different types of true-time delay structures are investigated for wideband phased array applications and a tunable S-band true-time delay network having delay over 1ns with high resolution is developed, designed, fabricated and measured. Lower-cost, smaller occupied area, digital/analog control mechanism and ease of implementation are the other features of the developed network. High delay values with high resolutions for wideband operation are achieved through the combination of several techniques / therefore the desired S-band TTD network is constructed with the synthesis of switched-transmission lines, constant-R networks and periodically-loaded transmission lines. Higher delay states are realized by the switched-transmission lines technique, while the method of constant R-network is used for the intermediate delay states. To increase the tuning flexibility, smaller delay states are accomplished by analog-voltage controlled periodically loaded transmission lines. A step-by-step procedure is followed during the design process of the S-band true time delay network. Firstly, each method used in the TTD network is analyzed in detail and developed for PCB implementation and the use of COTS components. Then, the designed structures are verified via linear and EM simulations performed by ADS2011&reg / . After that, the effects of production tolerances are examined to optimize each design for S-band operations. Moreover, the designed structures are fabricated by using PCB technology and measured. Finally, a software code is developed in MATLAB to generate the overall cascaded network with the help of measured data.

We investigate the linear stability and perform the bifurcation analysis for Hopfield neural networks with a general distribution of delays, where the neurons are identical. We start by analyzing the scalar model and show what kind of information can be gained with only minimal information about the exact distribution of delays. We determine a mean delay and distribution independent stability region. We then illustrate a way of improving on this conservative result by approximating the true region of stability when the actual distribution is not known, but some moments or cumulants of the distribution are. We compare the approximate stability regions with the stability regions in the case of the uniform and gamma distributions. We show that, in general, the approximations improve as more moments or cumulants are used, and that the approximations using cumulants give better results than the ones using moments. Further, we extend these results to a network of n identical neurons, where we examine the stability of a symmetrical equilibrium point via the analysis of the characteristic equation both when the connection matrix is symmetric and when it is not. Finally, for the scalar model, we show under what conditions a Hopf bifurcation occurs and we use the centre manifold technique to determine the criticality of the bifurcation. When the kernel represents the gamma distribution with p=1 and p=2, we transform the delay differential equation into a system of ordinary differential equations and we compare the centre manifold computation to the one we obtain in the ordinary differential case.

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

We investigate the linear stability and perform the bifurcation analysis for Hopfield neural networks with a general distribution of delays, where the neurons are identical. We start by analyzing the scalar model and show what kind of information can be gained with only minimal information about the exact distribution of delays. We determine a mean delay and distribution independent stability region. We then illustrate a way of improving on this conservative result by approximating the true region of stability when the actual distribution is not known, but some moments or cumulants of the distribution are. We compare the approximate stability regions with the stability regions in the case of the uniform and gamma distributions. We show that, in general, the approximations improve as more moments or cumulants are used, and that the approximations using cumulants give better results than the ones using moments. Further, we extend these results to a network of n identical neurons, where we examine the stability of a symmetrical equilibrium point via the analysis of the characteristic equation both when the connection matrix is symmetric and when it is not. Finally, for the scalar model, we show under what conditions a Hopf bifurcation occurs and we use the centre manifold technique to determine the criticality of the bifurcation. When the kernel represents the gamma distribution with p=1 and p=2, we transform the delay differential equation into a system of ordinary differential equations and we compare the centre manifold computation to the one we obtain in the ordinary differential case.

Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / This thesis presents a novel device for delaying Ethernet traffic in a lab setting. Ethernet is the leading standard for communications between computing devices. With the advent of streaming media such as voice over IP phone service and real-time control systems over Ethernet, applications are being rapidly developed that must meet strict communication reliability and timing constraints. Increasingly, these systems must be examined in real world scenarios before actual hardware deployment or protocol release. This increases the demand for both testing equipment and well trained network engineers. Commercial Ethernet delay testing devices are expensive, hardware specific, and not flexible enough for educational purposes. These short-comings make it necessary to design a robust Field Programmable Gate Array (FPGA) based Ethernet delay device that is up to the rigor of educational and research settings. Our approach is based on the inexpensive, high performance Altera Stratix II GX PCI Express development board which can easily be adapted for different delay scenarios. The system's FPGA hardware was developed in Verilog, an industry standard hardware description language, so users will be able to quickly learn, adapt and operate the system. Software for the system's soft processor was developed in C. The device provides a wide range of packet delay from nearly zero up to over fifty milliseconds, as well as providing an easy to use interface with on-the-fly variable delay adjustment. Theoretical throughput was up to 1Gb/s; skew and jitter measurements were comparable with common network switches. These properties allow the device to provide an easy-to-use, inexpensive method to delay Ethernet traffic in lab settings and the device also creates a starting point for future students and researchers to develop high speed traffic delay testbeds. Future work will include 10Gb/s throughput, additional memory capacity and additional software implemented delay profiles.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Delay-tolerant networking (DTN) is a system for constructing automated data networks in which end-to-end communication is reliable despite low data rates, possible sustained interruptions in connectivity, and potentially high signal propagation latency. As such it promises to provide an inexpensive and robust medium for returning telemetry from research vehicles in environments that provide meager support for communications: deep space, the surface of Mars, the poles or the sub- Arctic steppes of Earth, and others. This paper presents an overview of DTN concepts, including “bundles” and the Bundling overlay protocol. One possible scenario for the application of DTN to a telemetry return problem is described, and there is a brief discussion of the current state of DTN technology development.

The prevalence of procrastination in the college environment is extremely high with estimates that 80–90% of college students procrastinate when completing academic tasks. Since it impacts the majority of college students, early identification of an individual’s personality traits and behavioral delay discounting tendencies that may contribute to academic procrastination can lead to improved productivity and overall, a better college experience. The present study reviews what is already known about the relationships between personality and delay discounting with academic procrastination. Based on the review of the current literature, this study strives to reinforce and extend what is known about the relationships between these variables, improve the methodology used to examine these relationships, and provide a possible neural basis of procrastination. The proposed study will be conducted with first-year undergraduate student participants who attend Scripps College, over three academic terms (three participant samples). The study materials consist of two self-report personality measures (Myers-Briggs Type Indicator and Revised NEO Personality Inventory), a delay discounting task involving choices between hypothetical monetary rewards, and two measures of academic procrastination: a self-report measure (Procrastination Assessment Scale—Students) and a behavioral measure through course assignment submission. The study predicts that the typical academic procrastinator is introverted, perceptive, neurotic, and impulsive. In addition, an academic procrastinator has tendencies toward poor self-discipline, non-conscientious behavior, and preferences for discounted future rewards. Limitations of this study and future directions are also discussed.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper will describe a test technique developed to measure the delays caused by the use of asynchronous multiplexers/demultiplexers. These devices are used for both signal transmission (microwave and fiber optic) and signal recording (especially helical scan digital recorders). The test technique involves the generation and decoding of asynchronous telemetry signals. The bit rates of the telemetry signals are variable. Relative time is embedded in the telemetry signal as a 32-bit data word. The paper will also present measured delays for two multiplexers/demultiplexers for different combinations of bit rates.

published_or_final_version / Mechanical Engineering / Doctoral / Doctor of Philosophy