In recent years, Condition Monitoring (CM), which can be performed via several sensor channels, has been recognized as an effective paradigm for failure prevention of operational equipment or processes. However, the complexity caused by asynchronous data collection with different and/or time-varying sampling/transmission rates has long been a hindrance in the effective use of multichannel data in constructing empirical models. The problem becomes more challenging when sensor readings are incomplete. Traditional sensor data recovery techniques are often prohibited in asynchronous CM environments, not to mention sparse datasets. The proposed Functional Principal Component Analysis (FPCA) methodologies, e.g., nonparametric FPC model and semi-parametric functional regression model, provide new sensor data recovery techniques to improve the reliability and robustness of multichannel CM systems. Based on the FPCA results obtained from historical asynchronous data, the deviation from the smoothing trajectory of each sensor signal can be described by a set of unit-specific model parameters. Furthermore, the relationships among these sensor signals can be identified and used to construct regression models for the correlated signals. For real-time or online implementation, use of these models along with the parameters adjusted by real-time CM data become powerful tools for dealing with asynchronous CM data while recovering lost data when needed. To improve the robustness and predictability in dealing with asynchronous data, which may be skewed in probability distribution, robust methods were developed based on Functional Data Analysis (FDA) and Local Quantile Regression (LQR) models. Case studies examining turbofan aircraft engines and an experimental two-tank flow-control loop are used to demonstrate the effectiveness and adaptability of the proposed sensor data recovery techniques. The proposed methods may also find a variety of applications in systems of other industries, such as nuclear power plants, wind turbines, railway systems, economic fields, etc., which may face asynchronous sampling and/or missing data collection problems.

Enterprises today are dealing with extremely large amounts of critical digital information that continues to grow at an astonishing rate. On the other hand, storage software (firmware, middleware) and systems are becoming much more complex and existing failure recovery mechanisms are insufficient to handle the scale of these systems while meeting high availability and service quality expectations. In addition, the concurrent development and quality assurance processes, the large number of test scenarios and the large scale of these systems and services imply that failures will be the norm rather than the exception. Therefore achieving high availability and reliability in storage systems remains a major concern and an open research challenge. Most existing work in the domain of storage system availability addresses failures of the storage media (such as disks) and recoverability from these failures. However, failures at the firmware and middleware layers remain largely unaddressed. This dissertation research addresses these challenges in depth across different storage architectures. Concretely, we make the following contributions: First, we develop a recovery conscious framework for multi-core architectures and a suite of techniques for performing efficient fine-grained recovery (micro-recovery) in storage controller firmware that can be retrofitted into legacy code. The framework includes a task-level recovery mechanism, the Log(Lock) architecture that allows system state restoration during micro-recovery, and recovery-conscious scheduling algorithms that are designed to reduce the ripple effect of failure and improve recovery efficiency and system availability. Our second technical contribution addresses the storage middleware availability. We develop the notion of hierarchical middleware architectures by organizing critical cluster management services into a hierarchical overlay network, which separates persistent application state from global system control state and demonstrate significant improvement in the availability and reliability of enterprise scale storage systems. In addition, we develop the notion of operator reuse and a suite of reuse techniques to improve data availability. The key idea of operator reuse is to efficiently utilize system resources by exploiting reuse opportunities in both operators and persistent state of computing nodes. We demonstrate our design through STREAMREUSE, a reuse-conscious store-forward network of storage nodes, which offers distributed stream query processing services.

Análise sobre a estrutura e a organização da base de informações institucionais e estatísticas da Pesquisa Municipal Unificada PMU, sob a perspectiva da disponibilização de seus dados. As informações institucionais e estatísticas, em âmbito municipal, constituem importante subsídio para a gestão pública, devendo ser disseminadas aos executores dos setores governamentais, bem como aos representantes da sociedade civil organizada. Assim, são avaliados os processos de comunicação em sistemas informacionais e os referenciais para organização e tratamento das informações. Procura-se mostrar que o uso de procedimentos documentários e terminológicos pode melhorar as formas de disponibilização, o acesso e a apropriação da informação, concluindo-se que esses princípios devem ser incorporados às políticas de informação institucionais, como meio de otimizar a disponibilização e a recuperação das informações. / Analysis of the structure and organization of the data systems of the institutional and statistical data of the Unified Municipal Research (PMU), from the perspective of the availability of its data. Institutional and statistical data, in that concerning the municipality, provides vital assistance in the administration of public affairs and should be disseminated among administrators of government bodies, as well as representatives of organized civil society. Communication in information systems and the references for their organization and handling are thus evaluated. What is sought is to show that the use of documentary and terminological procedures can improve the means of data availability, as well as the accessing and appropriation of data. This leads to the conclusion that such principles should be incorporated into institutional information policies as a means to optimize data availability and recovery.

This diploma thesis is focused on the development of a new backup plan and its implementation. In introductory part of the thesis I explore the theorethical backround of data backup and data management. Next part is dedicated to analysis of current state and investor requierements. Last part is aimed to implementation of new backup plan with focusing on economic and quality point of view. Besides concept and realization of backup plan the concept of the backup directive is created .

This work relates to problematics of FAT32 file system metadata recovery from damaged flash drive or memory card and design of program capable of such recovery and comparision with existing solution for this task.

Incomplete data represents a major challenge for a successful prediction and subsequent removal of multiples. In this paper, a new method will be represented that tackles this challenge in a two-step approach. During the first step, the recenly developed curvelet-based recovery by sparsity-promoting inversion (CRSI) is applied to the data, followed by a prediction of the primaries. During the second high-resolution step, the estimated primaries are used to improve the frequency content of the recovered data by combining the focal transform, defined in terms of the estimated primaries, with the curvelet transform. This focused curvelet transform leads to an improved recovery, which can subsequently be used as input for a second stage of multiple prediction and primary-multiple separation.

Most modern clock and data recovery circuits (CDR) are based on analog blocks that need to be redesigned whenever the technology process is to be changed. On the other hand, CDR based blind oversampling architecture (BO-CDR) can be completely designed in a digital process which makes its migration very simple. The main disadvantages of the BO-CDR that are usually mentioned in a literature are complexity of its digital circuitry and finite phase resolution resulting in larger jitter sensitivity and higher error rate. This thesis will show that those problems can be solved by designing a new algorithm of BO-CDR and subsequent optimization. For this task an FPGA was selected as simulation and verification platform. This enables to change parameters of the optimized circuit in real time while measuring on real links (unlike a simulation using inaccurate link models). The output of this optimization is a new BO-CDR algorithm with heavily reduced complexity and very low error rate. A new FPGA-based method of jitter measurement was developed (primary for CDR analysis), which enables a quick link characterization without using probing or additional equipment. The new method requires only a minimum usage of FPGA resources. Finally, new measurement equipment was developed to measure bit error distribution on FSO links to be able to develop a suitable error correction scheme based on ARQ protocol.

Les circuits de récupération d'horloge et de données sont nécessaires au bon fonctionnement de plusieurs systèmes de communication sans fil. Les travaux effectués dans le cadre de cette thèse concernent le développement de ces circuits avec d'une part la réalisation, en technologie HCMOS9 0,13 μm de STMICROELECTRONICS, de circuits CDR analogiques à 1 et 54 Mbit/s, et d'autre part, la mise en œuvre de fonctions CDR numériques programmables à bas débit. Un circuit CDR fonctionnant à plus bas débit (1 Mbit/s) a été conçu dans le cadre de la gestion d'énergie d'un récepteur ULB impulsionnel non cohérent. Ces deux structures ont été réalisées à l'aide de PLL analogiques du 3ème ordre. Un comparateur de phase adapté aux impulsions issues du détecteur d'énergie a été proposé dans cette étude. Les circuits ont ensuite été dimensionnés dans le but d'obtenir de très bonnes performances en termes de jitter et de consommation. En particulier, les performances mesurées (sous pointes) du circuit CDR à 1 Mbit/s permettent d'envisager une gestion d'énergie efficace (réduction de plus de 97% de la consommation du récepteur). Dans le cadre d'une chaîne de télémesure avion vers sol, deux circuits CDR numériques ont également été réalisés durant cette thèse. Une PLL numérique du second degré a été implémentée en vue de fournir des données et une horloge synchrone de celles-ci afin de piloter une chaîne SOQPSK entièrement numérique. Un circuit ELGS a également mis au point pour fonctionner au sein d'un récepteur PCM/FM. / Clock and data recovery circuits are required in many wireless communication systems. This thesis is about development of such circuits with: firstly, the realization, in HCMOS9 0.13 μm of STMICROELECTRONICS technology, of 1 and 54 Mb/s analog CDR circuits, and secondly, the implementation of programmable digital circuits at low rates. In the aim of an impulse UWB transceiver dealing with video transmission, a CDR circuit at 54 Mb/s rate has been realized to provide clock signal synchronously with narrow pulses (their duration is about a few nanoseconds) from the energy detector. Another CDR circuit has been built at 1 Mb/s rate in a non-coherent IR- UWB receiver power management context. Both circuits have been implemented as 3rd order analog PLL. In this work, a phase comparator suitable for “RZ low duty cycle” data from the energy detector has been proposed. Circuits have been sized to obtain very good performances in terms of jitter and power consumption. Particularly, measured performances of the 1 Mb/s CDR circuit allow to plan an efficient power management (a decrease of more than 97% of the receiver total power consumption). In the context of a telemetry system from aircraft to ground, two digital CDR circuits have also been implemented. A second order digital PLL has been adopted in order to provide synchronous clock and data to an SOQPSK digital transmitter. Also, a digital ELGS circuit has been proposed to work in a PCM/FM receiver. For both CDR structures, the input signal rate is programmable and varies globally from 1 to 30 Mb/s.

CAPES / Em ensaios não destrutivos por ultrassom, o sinal obtido a partir de um sistema de aquisição de dados real podem estar contaminados por ruído e os ecos podem ter atrasos de tempo subamostrais. Em alguns casos, esses aspectos podem comprometer a informação obtida de um sinal por um sistema de aquisição. Para lidar com essas situações, podem ser utilizadas técnicas de estimativa de atraso temporal (Time Delay Estimation ou TDE) e também técnicas de reconstrução de sinais, para realizar aproximações e obter mais informações sobre o conjunto de dados. As técnicas de TDE podem ser utilizadas com diversas finalidades na defectoscopia, como por exemplo, para a localização precisa de defeitos em peças, no monitoramento da taxa de corrosão em peças, na medição da espessura de um determinado material e etc. Já os métodos de reconstrução de dados possuem uma vasta gama de aplicação, como nos NDT, no imageamento médico, em telecomunicações e etc. Em geral, a maioria das técnicas de estimativa de atraso temporal requerem um modelo de sinal com precisão elevada, caso contrário, a localização dessa estimativa pode ter sua qualidade reduzida. Neste trabalho, é proposto um esquema alternado que estima de forma conjunta, uma referência de eco e atrasos de tempo para vários ecos a partir de medições ruidosas. Além disso, reinterpretando as técnicas utilizadas a partir de uma perspectiva probabilística, estendem-se suas funcionalidades através de uma aplicação conjunta de um estimador de máxima verossimilhança (Maximum Likelihood Estimation ou MLE) e um estimador máximo a posteriori (MAP). Finalmente, através de simulações, resultados são apresentados para demonstrar a superioridade do método proposto em relação aos métodos convencionais. / Abstract (parágrafo único): In non-destructive testing (NDT) with ultrasound, the signal obtained from a real data acquisition system may be contaminated by noise and the echoes may have sub-sample time delays. In some cases, these aspects may compromise the information obtained from a signal by an acquisition system. To deal with these situations, Time Delay Estimation (TDE) techniques and signal reconstruction techniques can be used to perform approximations and also to obtain more information about the data set. TDE techniques can be used for a number of purposes in the defectoscopy, for example, for accurate location of defects in parts, monitoring the corrosion rate in pieces, measuring the thickness of a given material, and so on. Data reconstruction methods have a wide range of applications, such as NDT, medical imaging, telecommunications and so on. In general, most time delay estimation techniques require a high precision signal model, otherwise the location of this estimate may have reduced quality. In this work, an alternative scheme is proposed that jointly estimates an echo model and time delays for several echoes from noisy measurements. In addition, by reinterpreting the utilized techniques from a probabilistic perspective, its functionalities are extended through a joint application of a maximum likelihood estimator (MLE) and a maximum a posteriori (MAP) estimator. Finally, through simulations, results are presented to demonstrate the superiority of the proposed method over conventional methods.