Better methods and tools are needed in the fight against child pornography. This thesis presents a method for file type categorisation of unknown data fragments, a method for reassembly of JPEG fragments, and the requirements put on an artificial JPEG header for viewing reassembled images. To enable empirical evaluation of the methods a number of tools based on the methods have been implemented. The file type categorisation method identifies JPEG fragments with a detection rate of 100% and a false positives rate of 0.1%. The method uses three algorithms, Byte Frequency Distribution (BFD), Rate of Change (RoC), and 2-grams. The algorithms are designed for different situations, depending on the requirements at hand. The reconnection method correctly reconnects 97% of a Restart (RST) marker enabled JPEG image, fragmented into 4 KiB large pieces. When dealing with fragments from several images at once, the method is able to correctly connect 70% of the fragments at the first iteration. Two parameters in a JPEG header are crucial to the quality of the image; the size of the image and the sampling factor (actually factors) of the image. The size can be found using brute force and the sampling factors only take on three different values. Hence it is possible to use an artificial JPEG header to view full of parts of an image. The only requirement is that the fragments contain RST markers. The results of the evaluations of the methods show that it is possible to find, reassemble, and view JPEG image fragments with high certainty.

Data streams being transmitted over a network channel with capacity less than the data rate of the data streams is very common when using network channels such as dial-up, low bandwidth wireless links. Not only does this lower capacity creates delays but also causes sequential network problems such as packet losses, network congestion, errors in data packets giving rise to other problems and creating a cycle of problems hard to break out from. In this thesis, we present a new approach for shedding the less informative attribute data from a data stream with a fixed schema to maintain a data rate lesser than the network channels capacity. A scheme for shedding attributes, instead of tuples, becomes imperative in stream data where the data for one of the attributes remains relatively constant or changes less frequently compared to the data for the other attributes. In such a data stream management system, shedding a complete tuple would lead to shedding of some informative-attribute data along with the less informative-attribute data in the tuple, whereas shedding of the less informative-attribute data would cause only the less informative data to be dropped. In this thesis, we deal with two major problems in load shedding: the intra-stream load shedding and the inter-stream load shedding problems. The intra-stream load shedding problem deals with shedding of the less informative attributes when a single data stream with the data rate greater than the channel capacity has to be transmitted to the destination over the channel. The inter-stream load shedding problem refers to shedding of attributes among different streams when more than one stream has to be transferred to the destination over a channel with the channel capacity less than the combined data rate of all the streams to be transmitted. As a solution to the inter-stream or intra-stream load shedding problem, we apply our load shedding schema approach to determine a ranking amongst the attributes on a singe data stream or multiple data streams with the least informative attribute(s) being ranked the highest. The amount of data to be shed to maintain the data rate below the capacity is calculated dynamically, which means that the amount of data to be shed changes with any change in the channel capacity or any change in the data rate. Using these two pieces of information, a load shedding schema describing the attributes to be shed is generated. The load shedding schema is generated dynamically, which means that the load shedding schema is updated with any change in (i) the rankings of attributes that capture the rate of change on the values of each attribute, (ii) channel capacity, and (iii) data rate even after load shedding has been invoked. The load shedding schema is updated using our load shedding schema re-evaluation algorithm, which adapts to the data stream characteristics and follows the attribute data variation curve of the data stream. Since data dropped at the source may be of interest to the user at the destination, we also propose a recovery module which can be invoked to recover attribute data already shed. The recovery module maintains the minimal amount of information about data already shed for recovery purpose. Preliminary experimental results have shown that recovery accuracy ranges from 90% to 99%, which requires only 5% to 33% and 4.88% to 50% of the dropped data to be stored for weather reports and stock exchanges, respectively. Storing of recovery information imposes storage and processing burden on the source site, and our recovery method aims at satisfactory recovery accuracy while imposing minimal burden on the source site. Our load shedding approach, which achieves a high performance in reducing the data stream load, (i) handles wide range of data streams in different application domains (such as weather, stocks, and network performance, etc.), (ii) is dynamic in nature, which means that the load shedding scheme adjusts the amount of data to be shed and which attribute data to be shed according to the current load and network capacity, and (iii) provides a data recovery mechanism that is capable to recover any shedded attribute data with recovery accuracy up to 90% with very low burden on the source site and 99% with a higher burden on some stream data. To the best of our knowledge, the dynamic load shedding scheme we propose is the first one in the literature to shed attributes, instead of tuples, along with providing a recovery mechanism in a data stream management system. Our load shedding approach is unique since it is not a static load shedding schema, which is less appealing in an ever-changing (sensor) network environment, and is not based on queries, but works on the general characteristics of the data stream under consideration instead.

Análise sobre a estrutura e a organização da base de informações institucionais e estatísticas da Pesquisa Municipal Unificada PMU, sob a perspectiva da disponibilização de seus dados. As informações institucionais e estatísticas, em âmbito municipal, constituem importante subsídio para a gestão pública, devendo ser disseminadas aos executores dos setores governamentais, bem como aos representantes da sociedade civil organizada. Assim, são avaliados os processos de comunicação em sistemas informacionais e os referenciais para organização e tratamento das informações. Procura-se mostrar que o uso de procedimentos documentários e terminológicos pode melhorar as formas de disponibilização, o acesso e a apropriação da informação, concluindo-se que esses princípios devem ser incorporados às políticas de informação institucionais, como meio de otimizar a disponibilização e a recuperação das informações. / Analysis of the structure and organization of the data systems of the institutional and statistical data of the Unified Municipal Research (PMU), from the perspective of the availability of its data. Institutional and statistical data, in that concerning the municipality, provides vital assistance in the administration of public affairs and should be disseminated among administrators of government bodies, as well as representatives of organized civil society. Communication in information systems and the references for their organization and handling are thus evaluated. What is sought is to show that the use of documentary and terminological procedures can improve the means of data availability, as well as the accessing and appropriation of data. This leads to the conclusion that such principles should be incorporated into institutional information policies as a means to optimize data availability and recovery.

This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.