Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.

Though erasure codes are widely adopted in high fault tolerance storage systems, there exists a serious small-write problem. Many algorithms are proposed to improve small-write performance in RAID systems, without considering the network bandwidth usage. However, the network bandwidth is expensive in cloud systems. In this thesis, we proposed an ECL-based (E-MBR codes, Caching and Logging-based) technique to improve the small-write performance without using extra network bandwidth. In addition, the ECL-based technique also reduces the delayed parity update and data recovery latency compared with the competing algorithm.

Nachdem in kurzer Folge zwei Medien auf meinen Tisch gelangten, auf denen bis vor kurzem viele schöne Bilder gespeichert waren, die man nun aber nicht mehr finden konnte, unternahm ich erste vorsichtige Ausflüge in das Gebiet der Datenrettung. Die Wege und Werkzeuge, die letztendlich zum Erfolg führten, sollen in einem kurzen Vortrag vorgestellt werden.

Thesis (M.S.)--University of Hawaii at Manoa, 2004. / Includes bibliographical references (leaves 64-66). Also available via World Wide Web.

Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Ling Liu; Committee Member: Brian Cooper; Committee Member: Calton Pu; Committee Member: Douglas Blough; Committee Member: Karsten Schwan. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.

No description available.

Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 70-71). Also available in electronic format on the Internet.

Thesis (M.S.)--Ohio University, August, 1997. / Title from PDF t.p.

Thesis (Ph.D.) -- University of Rhode Island, 2009. / Typescript. Includes bibliographical references (leaves 128-137).