This thesis covers design and implementation of a media system solution for home networks with personal computers and a set-top box. In a home there are effectively two independent media systems with the same purpose: the personal computer and the digital set-top box, with the purpose of delivering digital media in form of audio and video to the consumer. The goal of the thesis work was to implement a solution that bridges the gap between the two systems, so that the user, from the set-top box, can play back media that is actually stored on one or several personal computers. Our solution is based on UPnP technology, which is used for service discovery and control. The choice of UPnP is motivated by an evaluation of discovery protocols, which concludes that UPnP is the most suitable technology in this particular system. Also, an evaluation of suitable transport protocols was done. Here,HTTP was used. For the personal computer, a media server and a graphical user interface for configuring the media server were created. For the set-top box, a media client, and a graphical user interface for browsing the content of the media server, were created. In conclusion, the creation of the prototype was successful and the set-top box was able to playback media that had been shared by the PC on the network.

Embedded computing systems in portable devices need to be energy efficient, yet they have to deliver adequate performance to the often computationally expensive applications. Dynamic voltage scaling is a technique that offers a speed versus power trade-off, allowing the application to achieve considerable energy savings and, at the same time, to meet the imposed time constraints. In this thesis, we explore the possibility of using optimal voltage scaling algorithms based on nonlinear programming at the system level, for a complex multiprocessor scheduling problem. We present an optimization approach to the modeled nonlinear programming formulation of the continuous voltage selection problem excluding the consideration of transition overheads. Our approach achieves the same optimal results as the previous work using the same model, but due to its speed, can be efficiently used for design space exploration. We validate our results using numerous automatically generated benchmarks.

The video game and esports industry has grown exponentially over the past few years.“During recent years, esports have become one of the most rapidly growing forms ofnew media driven by the growing provenance of online games and onlinebroadcasting technologies” (Hamari and Sjöblom, 2017). Sponsors have identifiedmarketing opportunities in this rapidly growing advertising medium. Brand placementin esports is gaining momentum as a means to target audiences in an indirect andengaging way. In our study we have defined embedded brand placement in the contextof video games and esports as the practice of including a brand name, signage or otherforms of trademark merchandise integrated naturally within the game and in return,visibly featured in the esport broadcast. The aim of this study was to examine howembedded brand placement performed during different spectating scenarios whichpossess different distraction levels and in-game dynamics (audio and visual). Ourstudy explores the effectiveness of embedded brand placement within esports byemploying an eye tracking methodology as well as a brand recall exercise inconnection to participant's prior involvement with the video game, League of Legendsand the respective esports scene. The practical implications from the results of thisstudy hope to assist advertisers in making a better informed decision aboutcollaborating with esport events and uncover a better perception in regards to howthey might expect their advertising messages to perform. Through our study, we havesuccessfully contributed to the foundation of research surrounding embedded brandplacements within esports through our investigation of practical factors affecting towhich extent viewers are able to consume these advertising messages. These factorsbeing prior involvement, how differing spectating scenarios, distractions and in-gamedynamics affect fixations on advertising messages and finally how the above factorscontribute to overall brand recall as well as long-term versus short-term brandrecollection.

<p>This master’s thesis examines the possibility to heuristically optimise instruction cache performance in a Just-In-Time (JIT) compiler. </p><p>Programs that do not fit inside the cache all at once may suffer from cache misses as a result of frequently executed code segments competing for the same cache lines. A new heuristic algorithm LHCPA was created to place frequently executed code segments to avoid cache conflicts between them, reducing the overall cache misses and reducing the performance bottlenecks. Set-associative caches are taken into consideration and not only direct mapped caches. </p><p>In Ahead-Of-Time compilers (AOT), the problem with frequent cache misses is often avoided by using call graphs derived from profiling and more or less complex algorithms to estimate the performance for different placements approaches. This often results in heavy computation during compilation which is not accepted in a JIT compiler. </p><p>A case study is presented on an Alpha processor and an at Ericsson developed JIT Compiler. The results of the case study shows that cache performance can be improved using this technique but also that a lot of other factors influence the result of the cache performance. Such examples are whether the cache is set-associative or not; and especially the size of the cache highly influence the cache performance.</p>

<p>A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed. </p><p>We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory. </p><p>We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way. </p><p>The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.</p>

<p>Software engineering tools are being used in the industry in order to improve the productivity and the quality of the software development process. The properties of those tools are being perceived to be unsatisfactory. For example, researchers have found that some problems are due to deficient integration among the tools. Furthermore, a continuing problem is that there is a gap between the IT education and real demand of tool-skills form IT industry. Consequently, knowledge is needed of the properties of software development tools as well an understanding of demanded tool-skill from the industry. </p><p>The purpose of this study is to survey commercial software development environment (SDEs) that are used today in professional software engineering and discuss their advantages adn disadvantages. A secondary goal of the study is to identify the actual requirements from the industry on the IT-education. </p><p>A questionnaire was sent out to 90 software developers and IT managers of 30 IT companies in Sweden. The results of the survey show that IT companies, for most part, use SDEs from commercial software vendors. Respondents report that common problems of the SDEs are the following: bad integration among the tools, problems to trace software artifacts in the different phases of the programming cycle, and deficient support for version control and system configuration. Furthermore, some tools are difficult to use which results in a time-consuming development process. </p><p>We conclude that future software development environments need to provide better support for integration, automation, and configuration management. Regarding the required tool-skills, we believe that the IT education would gain from including commercial tools that cover the whole software product lifecycle in the curriculum.</p>

<p>The technology today makes it possible to integrate a complete system on a single chip, called "System-on-Chip'' (SOC). Nowadays SOC designers use previously designed hardware modules, called cores, together with their user defined logic (UDL), to form a complete system on a single chip. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips. </p><p>The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. However, this will result in a higher activity in the chip, hence higher power consumption. Due to several factors in the manufacturing process there are limitations of the power consumption for a chip. Therefore, the power limitations should be carefully considered when planning the testing of a chip. Otherwise it can be damaged during test, due to overheating. This leads to the problem of minimizing testing time under such power constraints. </p><p>In this thesis we discuss test power modeling and its application to SOC testing. We present previous work in this area and conclude that current power modeling techniques in SOC testing are rather pessimistic. We therefore propose a more accurate power model that is based on the analysis of the test data. Furthermore, we present techniques for test pattern reordering, with the objective of partitioning the test power consumption into low parts and high parts. </p><p>The power model is included in a tool for SOC test architecture design and test scheduling, where the scheduling heuristic is designed for SOCs with fixed- width test bus architectures. Several experiments have been conducted in order to evaluate the proposed approaches. The results show that, by using the presented power modeling techniques in test scheduling algorithms, we will get lower testing times and thus lower test cost.</p>

This master’s thesis examines the possibility to heuristically optimise instruction cache performance in a Just-In-Time (JIT) compiler. Programs that do not fit inside the cache all at once may suffer from cache misses as a result of frequently executed code segments competing for the same cache lines. A new heuristic algorithm LHCPA was created to place frequently executed code segments to avoid cache conflicts between them, reducing the overall cache misses and reducing the performance bottlenecks. Set-associative caches are taken into consideration and not only direct mapped caches. In Ahead-Of-Time compilers (AOT), the problem with frequent cache misses is often avoided by using call graphs derived from profiling and more or less complex algorithms to estimate the performance for different placements approaches. This often results in heavy computation during compilation which is not accepted in a JIT compiler. A case study is presented on an Alpha processor and an at Ericsson developed JIT Compiler. The results of the case study shows that cache performance can be improved using this technique but also that a lot of other factors influence the result of the cache performance. Such examples are whether the cache is set-associative or not; and especially the size of the cache highly influence the cache performance.

A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed. We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory. We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way. The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.

Software engineering tools are being used in the industry in order to improve the productivity and the quality of the software development process. The properties of those tools are being perceived to be unsatisfactory. For example, researchers have found that some problems are due to deficient integration among the tools. Furthermore, a continuing problem is that there is a gap between the IT education and real demand of tool-skills form IT industry. Consequently, knowledge is needed of the properties of software development tools as well an understanding of demanded tool-skill from the industry. The purpose of this study is to survey commercial software development environment (SDEs) that are used today in professional software engineering and discuss their advantages adn disadvantages. A secondary goal of the study is to identify the actual requirements from the industry on the IT-education. A questionnaire was sent out to 90 software developers and IT managers of 30 IT companies in Sweden. The results of the survey show that IT companies, for most part, use SDEs from commercial software vendors. Respondents report that common problems of the SDEs are the following: bad integration among the tools, problems to trace software artifacts in the different phases of the programming cycle, and deficient support for version control and system configuration. Furthermore, some tools are difficult to use which results in a time-consuming development process. We conclude that future software development environments need to provide better support for integration, automation, and configuration management. Regarding the required tool-skills, we believe that the IT education would gain from including commercial tools that cover the whole software product lifecycle in the curriculum.