Cette thèse de doctorat étudie le nouveau concept de décodeur intelligent (SDec) dans lequel le décodeur est doté de la possibilité de simuler l’encodeur et est capable de mener la compétition R-D de la même manière qu’au niveau de l’encodeur. Cette technique vise à réduire la signalisation des modes et des paramètres de codage en compétition. Le schéma général de codage SDec ainsi que plusieurs applications pratiques sont proposées, suivis d’une approche en amont qui exploite l’apprentissage automatique pour le codage vidéo. Le schéma de codage SDec exploite un décodeur complexe capable de reproduire le choix de l’encodeur calculé sur des blocs de référence causaux, éliminant ainsi la nécessité de signaler les modes de codage et les paramètres associés. Plusieurs applications pratiques du schéma SDec sont testées, en utilisant différents modes de codage lors de la compétition sur les blocs de référence. Malgré un choix encore simple et limité des blocs de référence, les gains intéressants sont observés. La recherche en amont présente une méthode innovante qui permet d’exploiter davantage la capacité de traitement d’un décodeur. Les techniques d’apprentissage automatique sont exploitées pour but de réduire la signalisation. Les applications pratiques sont données, utilisant un classificateur basé sur les machines à vecteurs de support pour prédire les modes de codage d’un bloc. La classification des blocs utilise des descripteurs causaux qui sont formés à partir de différents types d’histogrammes. Des gains significatifs en débit sont obtenus, confirmant ainsi le potentiel de l’approche. / This Ph.D. thesis studies the novel concept of Smart Decoder (SDec) where the decoder is given the ability to simulate the encoder and is able to conduct the R-D competition similarly as in the encoder. The proposed technique aims to reduce the signaling of competing coding modes and parameters. The general SDec coding scheme and several practical applications are proposed, followed by a long-term approach exploiting machine learning concept in video coding. The SDec coding scheme exploits a complex decoder able to reproduce the choice of the encoder based on causal references, eliminating thus the need to signal coding modes and associated parameters. Several practical applications of the general outline of the SDec scheme are tested, using different coding modes during the competition on the reference blocs. Despite the choice for the SDec reference block being still simple and limited, interesting gains are observed. The long-term research presents an innovative method that further makes use of the processing capacity of the decoder. Machine learning techniques are exploited in video coding with the purpose of reducing the signaling overhead. Practical applications are given, using a classifier based on support vector machine to predict coding modes of a block. The block classification uses causal descriptors which consist of different types of histograms. Significant bit rate savings are obtained, which confirms the potential of the approach.

The main subject of this thesis is creating a programme, used for channel coding demonstration. This programme will be used for teaching purposes. The programme contains various codes from simple ones, to those which almost reach Shanon’s channel capacity theorem. Specifically these are the Hamming code, cyclic code, convolutional code and LDPC code. These functions are based on theoretical background described in this thesis and have been programed in Matlab. Practical output of this thesis is user interface, where the user is able to input information word, simulate transmission through the transmission channel and observe coding and decoding for each code. This thesis also contains a comparison between individual codes, concerning bit-error rate depending on SNR and various parameters. There is a computer lab with theoretical background, assignment and sheets for convenient accomplishment of each task.

This Master´s thesis discuses the protection of data transmission against long error bursts. The data is transmited throught the channel with defined error rate. Parameters of the channel are error-free interval 2000 bits and length of burst error 250 bits. One of the aims of this work is to make a set of possible methods for the realization of a system for data correction. The basic selection is made from most known codes. These codes are divided into several categories and then the best one is chosen for higher selection. Of course interleaving is used too. Only one code from each category can pass on to the higher level of the best code selection. At the end the codes are compared and the best three are simulated using the Matlab program to check correct function. From these three options, one is chosen as optimal regarding practical realization. Two options exist, hardware or software realization. The second one would seem more useful. The real codec is created in validator language C. Nowadays, considering language C and from a computer architecture point of view the 8 bits size of element unit is convenient. That´s why the code RS(255, 191), which works with 8 bits symbols, is optimal. In the next step the codec of this code is created containing the coder and decoder of the code above. The simulation of error channel is ensured by last program. Finally the results are presented using several examples.

The diploma thesis is focused on the measurement of selected parameters of the digital TV receiver DVB T, set top box. In the introductory part the work briefly deals with the theory of compression and transmission of the digital TV signal. Main part of the thesis contains detail information about individual circuits of the selected set top box Humax F3-FOX T and the results of measurements of individual parameters obtained from the available measuring devices. The final part of the thesis deals with the design changes necessary for creation of the external output for the signals and also with the methodology of the measurement.

This thesis is focused on a receiver for digital television broadcasting set-top box, mainly on its features, parameters and measurement. The important point of this work is the possibility to analyze and visualize the parallel transport stream in the same time and the solution of this problem. The principle of tuner and its measuring is deeply discussed. The text is supported with oscilloscope screenshots in particular parts of decoding stream. The set-top box is modified for laboratory measurement purpose and the transport stream output is added. An example laboratory exercise was created as a part of this work.

The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.

The high demand of the video decoding has pushed the developers to implement the decoders on parallel architectures. This thesis provides the deliberations about the implementation of an MPEG-4 decoder on a massively parallel processor array (MPPA), Ambric 2045, by converting the CAL actor language implementation of the decoder. This decoder is the Xilinx model of the MPEG-4 Simple Profile decoder and consists of four main blocks; parser, acdc, idct2d and motion. The parser block is developed in another thesis work [20] and the rest of the decoder, which consists of the other three blocks, is implemented in this thesis work. Afterwards, in order to complete the decoder, the parser block is combined with the other three blocks. Several methods are developed for conversion purposes. Additionally, a number of other methods are developed in order to overcome the constraints of the ambric architecture such as no division support. At the beginning, for debugging purposes, the decoder is implemented on a simulator which is designed for Ambric architecture. Finally the implementation is uploaded to the Ambric 2045 chip and tested with different input streams. The performance of the implementation is analyzed and satisfying results are achieved when compared to the standards which are in use in the market. These performance results can be considered as satisfying for any real-time application as well. Furthermore, the results are compared with the results of the CAL implementation, running on a single 2GHz i7 intel processor, in terms of speed and efficiency. The Ambric implementation runs 4,7 times faster than the CAL implementation when a small input stream (300 frames with resolution of 176x144) is used. However, when a large input stream (384 frames with resolution of 720x480) is used, the Ambric implementation shows a performance which is approximately 32 times better than the CAL implementation, in terms of decoding speed and throughput. The performance may increase further together with the size of the input stream up to some point.

As an efficient energy storage technology, lithium-ion batteries play a key role in the ongoing electrification of the mobility sector. However, the required modelbased design process, including hardware in the loop solutions, demands precise battery models. In this work, an encoder-decoder model framework based on recurrent neural networks is developed and trained directly on unstructured battery data to replace time consuming characterisation tests and thus simplify the modelling process. A manifold pseudo-random bit stream dataset is used for model training and validation. A mean percentage error (MAPE) of 0.30% for the test dataset attests the proposed encoder-decoder model excellent generalisation capabilities. Instead of the recursive one-step prediction prevalent in the literature, the stage-wise trained encoder-decoder framework can instantaneously predict the battery voltage response for 2000 time steps and proves to be 120 times more time-efficient on the test dataset. Accuracy, generalisation capability and time efficiency of the developed battery model enable a potential online anomaly detection, power or range prediction. The fact that, apart from the initial voltage level, the battery model only relies on the current load as input and thus requires no estimated variables such as the state-of-charge (SOC) to predict the voltage response holds the potential of a battery ageing independent LIB modelling based on raw BMS signals. The intrinsically ageingindependent battery model is thus suitable to be used as a digital battery twin in virtual experiments to estimate the unknown battery SOH on purely BMS data basis.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Today’s telemetry systems can reduce spectrum demand and maintain secure voice by encoding analog voice into digital data using; Continuously Variable Slope Delta Modulation ( CVSD ) format and imbedding it into a telemetry stream. The model CSC-0390 DvD system is an excellent choice in decoding digital voice, designed with flexibility, efficiency, and simplicity in mind. Flexibility in design brings forth a capability of operating on a wide variety of telemetry systems and data formats without any specialized interfaces. The utilization of 74HC series circuit technology makes this DvD system efficient in design, low cost, and lower power consumption. In addition the front panel display and control function is also is an example of Simplicity in design and operation.

In 2008, the European Digital Video Broadcasting (DVB) standardization committee issued the second generation of Digital Video Broadcasting-Terrestrial (DVB-T2) standard in order to enable the wide broadcasting of high definition and 3D TV programmes. DVB-T2 has adopted several new technologies to provide more robust reception compared to the first genaration standard. One important technology is the bit interleaved coded modulation (BICM) with doubled signal space diversity plus the usage of low-density parity check (LDPC) codes. Both techniques can be combined at the receiver side through an iterative process between the decoder and demapper in order to further increase the system performance. The object of my study was to design and prototype a DVB-T2 receiver which supports iterative process. The two main contributions to the demapper design are the proposal of a linear approximation of Euclidean distance computation and the derivation of a sub-region detection algorithm for the two-dimensional demapper. Both contributions allows the computational complexity of the demapper to be reduced for its hardware implementation. In order to enable iterative processing between the demapper and the decoder, we investigated the use of vertical shuffled Min-Sum LDPC decoding algorithm. A novel vertical shuffled iterative structure aiming at reducing the latency of iterative processing and the corresponding architecture of the decoder were proposed. The proposed demapper and decoder have been integrated in a real DVB-T2 demodulator and tested in order to validate the efficiency of the proposed architecture. The prototype of a simplified DVB-T2 transceiver has been implemented, in which the receiver supports both non-iterative process and iterative process. We published the first paper related to a DVB-T2 iterative receiver.