Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 146-158). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 49-53).

Finally, we present a novel algorithm for intruder detection in a sinkhole attack of wireless sensor network. The algorithm can identify the intruder and deal with multiple malicious nodes effectively. We have evaluated the performance of the proposed algorithm through both numerical analysis and simulations, which confirmed the effectiveness and accuracy of our algorithm. / In this thesis, we propose a general reliability-centric framework for event reporting in WSANs. We point out that the reliability in such a real-time system depends not only on the accuracy, but also the importance and freshness of the reported data. Our proposed design thus integrates three key modules, (1) an efficient and fault-tolerant event data aggregation algorithm, (2) a delay-aware data transmission protocol, and (3) an adaptive actuator allocation algorithm for unevenly distributed events. We further propose a latency-oriented fault tolerant data transport protocol (LOFT) and a power-controlled real-time data transport protocol (POWER-SPEED) for WSANs. LOFT balances the workload of sensors by checking their queue utilization and handles node/link failures by an adaptive replication algorithm. POWER-SPEED transmits packets in an energy-efficient manner while maintaining soft real-time packet transport. We evaluate our framework and the two proposed protocols through extensive simulations, and the results demonstrate that they achieve the desirable reliability for WSANs. / To minimize the data collection time, we propose a new routing design. We present the mathematical formulation of the route design problem, and show that it is computationally intractable. We then propose two practical algorithms to reduce the delay of the sensors. Our algorithms adaptively adjust the actuator visiting frequencies to the sensors according to their relative weights and data generation patterns. We further propose a probabilistic route design (PROUD) algorithm which adapts to network dynamics. We present the distributed implementation for PROUD and an extension which accommodates actuators with variable speeds. We also propose algorithms for load balancing among the actuators. Simulation results show that our algorithms can effectively reduce the overall data collection time. They adapt to the network dynamics and balances the energy consumption of the actuators. / Wireless sensor-actuator networks, or WSANs, greatly enhance the existing wireless sensor network architecture by introducing powerful and mobile actuators. These actuators are expected to work with the sensor nodes and perform much richer application-specific actions. For the applications which request for fast and accurate report of the environmental events, an efficient and reliable communication/coordination scheme is urged. Unfortunately, multi-hop communication in a WSAN is inherently unreliable due to frequent sensor failures and network partitions. Excessive delays, introduced by congestion or in-network data aggregation, further aggravate the problem. / Ngai, Cheuk Han. / "August 2007." / Adviser: Michael R. Lyu. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1113. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 191-207). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.

Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references (p.68-73).

With advances in technology, modern integrated circuits have higher complexities and reduced transistor sizing. In deep sub-micron, the parameter variation-control is difficult and component delays vary from one manufactured chip to another. Therefore, the delays are not discrete values but are a statistical quantity, and statistical evaluation methods have gained traction. Furthermore, fault injection based gate-level fault coverage is non-scalable and statistical estimation methods are preferred. This dissertation focuses on scalable statistical methods to select critical paths in the presence of process variations, and to improve the defect coverage for complex integrated circuits. In particular, we investigate the sensitization probability of a path by a test pattern under statistical delays. Next, we investigate test pattern generation for improving the sensitization probability of a path, selecting critical paths that yield high defect coverage, and scalable method to estimate fault coverage of complex designs using machine learning techniques.

Šiais laikais naujos technologijos sudaro vis didesnę mūsų gyvenimo dalį, bet jų jau greičiausiai neįsivaizduotume savęs. Tačiau ne visi naujų tachnologijų kūriniai tarnauja ilgai, taip pat kaip ne visi jie veikia teisingai. Tam, kad nustatytume, jog įrenginys veikia teisingai raikalinga atlikti testavimą. Mažėjant schemų dydžiams, augant metalo tankiui ir didėjant lustų veikimo greičiui, vėlinimų testavimas tampa būtinybe tam, kad palaikyti kokybę susijusią su schemos veikimo greičių sutrikimais. Vėlinimo gedimų tyrimas atsako į klausimą ar schema veikia teisingai be didelių nuostolių. Šiame darbe aptarsime vėlinimo gedimų atsiradimo priežastis bei galimas juos įtakojančias sąlygas. Taip pat analizuosime vėlinimo gedimų testavimo modelius, metodus, jų privalumus, trūkumus ir galimus trūkumų sprendimus. Tyrimui pilnai atlikti inicijuosime eksperimentą, siekdami išsiaiškinti tiesioginės ir netiesioginės įtakos poveikį vėlinimų gedimų funkciniam testui. / Nowadays new technologies contains the bigger part of our lifes, we couldnt imagine our selves without them. Otherwise, not all creations of new technologies are serving so long, also not all of them are serving right and effectively. When the system size degrees, the metal grows, and the time working on chips grows – the delay fault testing becomes very important part of system creation process. The delay fault test answers to the question does the system works right and without any big loses. The test process has important point in Delay test has been investigated for many years. We can say that test process contains on these steps: setting the purpose of the test, designing the test, controlling the test process, perform the test and analyze test results. Also we will shortly discuss about basic gauge of testing process. The main point of this paper is to analyze the models of delay faults test processes. To see the best and the worst sides of delay faults and represent experimental test to demonstrate the the robust and non-robust test advantagies in delay fault test.

Šio darbo tikslas yra realizuoti ir ištirti funkcinių vėlinimo testų generavimo algoritmus. Gaminant programuojamuosius įrenginius visada atsiranda galimybė jog gali atsirasti vėlinimo klaidų ( įėjimo signalas dėl kažkokių priežasčių išeina vėliau nei yra numatyta ). Šiuo metu lustai naudojami civilinėje bei karinėje pramonėje įvairiems gamybos procesams valdyti, pvz: medicinoje. Vėlinimo gedimų testavimai yra labai reikšmingi tiek sistemų saugumo užtikrinime, tiek sistemos patikimumo atžvilgiu. Šiais laikais tokie reikalavimai yra keliami vis didesni, nes žmogaus saugumas yra visų svarbiausia. Realizuojamas funkcinis vėlinimo testo sudarymo algoritmas pagal pokyčius išėjimuose, kuris remiasi tik programinio prototipo pirminių įėjimų ir pirminių išėjimų reikšmėmis. Sukūrus sistemą, buvo atliktas eksperimentinis jos tyrimas. Gauti panaudoto algoritmo rezultatai yra patenkinami, kurie yra pateikti šio dokumento priede. Eksperimento metu atliekami testinių rinkinių generavimai 24 loginėms schemoms. Darbe yra 42 panaudoti paveikslėliai, 27 lentel��s bei santrumpų žodynas. Medžiaga surinkta iš penkiolikos literatūros šaltinių. / The object of this work is to research functional test generation methods for delay faults. Manufacturing of programmable chips always has possibility that in those systems will be delay faults that means: input signal for some reasons appear in the output after longer time than the time was definite. In our days, programmable chips are used in the industry for the management of various civil and military manufacturing processes, for instance medicine. Delay fault testing is very important part for the system safety and trustiness. Today those requests become higher and higher, because human safety is common importance. Created test generation algorithm of the functional test that is based solely on the primary input values and the primary output values of the programming prototype. System was tested by simple step by step model,(which is presented in the fourth part of this document). The obtained results are useful and acceptable. All results are presented in the appendix of this document. The experiment contains 24 logic schemas processed test generation algorithm. The work includes of 42 pictures, 27 tables and conceptual dictionary. 15 bibliographical sources have been used.

Dissertation (Ph.D.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references (p.107-111).

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (leaves 59-60).

Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e testabilidade. Normalmente estes algoritmos conseguem uma relação de compromisso para a otimização de dois critérios. Efeitos indesejáveis também podem surgir com a otimização de um destes critérios. Por exemplo, as otimizações de desempenho podem introduzir falhas de colagem não testáveis (redundâncias) em um circuito, reduzindo a sua testabilidade. Muitos algoritmos de síntese lógica exploram propriedades específicas de determinadas funções a serem sintetizadas. Um exemplo de função com propriedades específicas são as funções ditas unate. Um exemplo deste tipo de função é o sinal de carry de um somador completo. Este tipo de função exige cuidados especiais para evitar a introdução de redundâncias. Muitos dos algoritmos para síntese lógica empregam a decomposição de Shannon para melhorar o desempenho de um circuito. A equação geral da decomposição de Shannon é expressa através de uma função binate. As redundâncias sempre serão introduzidas nos circuitos quando uma equação binate é utilizada para representar uma função unate. Diagramas de Decisão Binária (BDDs) são um tipo estruturas de dados muito utilizadas em algoritmos para síntese lógica. A decomposição de Shannon também é utilizada para derivar circuitos a partir de BDDs. Este tipo de estrutura representa uma função lógica, mas não mantém uma representação sem redundâncias da mesma. Infelizmente, os circuitos derivados a partir desta estrutura poderão ser redundantes, principalmente quando a decomposição de Shannon for utilizada. Existem estruturas de dados capazes de representar uma função sem redundâncias. Este é o caso dos VPBDDs , que possuem propriedades especiais que preservam características de testabilidade da função representada. Baseando-se nas propriedades dos VPBDDs, um novo algoritmo para remoção de redundâncias foi proposto. Este algoritmo é capaz de gerar circuitos sem redundâncias, mesmo quando a função, que é representada pelo VPBDD, é unate. Além da geração de circuitos sem redundâncias, o algoritmo garante que o atraso do circuito não aumenta após a remoção de redundâncias. A área dos circuitos resultantes pode aumentar, diminuir ou permanecer a mesma, considerando o número de portas lógicas utilizadas. Todos os resultados obtidos neste trabalho mostram que o algoritmo consegue realizar a remoção de redundâncias, sem prejudicar o atraso do circuito. Além disso, todos os caminhos redundantes do circuito têm seu atraso reduzido, pois com a remoção de redundâncias o número de portas lógicas em série é reduzido. A aplicação deste algoritmo apresenta bons resultados para circuitos aritméticos. Isto se deve principalmente ao fato do carry ser uma função unate, o que pode introduzir redundâncias no circuito se esta propriedade (de ser unate) não for tratada adequadamente. O algoritmo proposto também abre possibilidades para a criação de outras ferramentas de CAD, como por exemplo: uma ferramenta para análise de timing, um gerador de circuitos aritméticos sem redundâncias, ou ainda uma ferramenta para geração de teste, incluindo lista de falhas, vetores de teste e cobertura de falhas. / Algorithms for digital circuit design aim the reduction of a cost function composed of four criteria: area, delay, power and testability. Usually these algorithms are able to obtain a trade-off for the optimization of two of these criteria. Undesired effects may occur due to the optimization of one of the criteria. For instance, delay optimizations may introduce non testable stuck-at faults (redundancies) in a circuit, this way reducing its testability. Several logic synthesis algorithms exploit specific properties of the logic functions to be synthesized. One example of function with specific properties are the socalled unate functions. An example of this kind of function is the carry-out sign in a full adder circuit. This kind of function require special care in order to avoid redundancy introduction. Shannon decomposition [SHA 38] is used in many logic synthesis algorithms for improving circuit performance. The general case of the Shannon decomposition is represented by a binate (not unate) equation. Redundancies are introduced in a circuit when a binate equation is used to express a unate function. Binary Decision Diagrams (BDDs) are a kind of data structures widely used in the field of logic synthesis. Shannon decomposition is also used to derive circuits from BDDs. This data structure is used to represent logic functions, but it is not able to maintain an irredundant representation of any logic function. Unfortunately, circuits derived from BDDs will possibly have redundancies, specially when Shannon decomposition is used. Some data structures are able to represent any logic function in a irredundant form. This is the case of the VPBDDs [REI 95a] [REI 2000], which have special properties that preserve the testability properties of the functions being represented. Based on VPBDD properties, a novel algorithm for redundancy removal was proposed [MAR 2002]. This algorithm is able to generate irredundant circuits even when the function represented by the VPBDD is unate. In addition to the generation of irredundant circuits, the algorithm guarantees that the circuit delay will not be increased by redundancy removal. The final area may be increased, reduced or even remain the same, considering the number of logic gates. The results obtained in this work indicate that the algorithm is able to perform redundancy removal without increasing the circuit delay. Besides, all the redundant paths in the circuit have their delay reduced, as the number of logic gates in series will be reduced by the redundancy removal process. The application of this algorithm gives good results for arithmetic circuits. This is mainly due to the fact that the carry chain is composed of unate functions, this way redundancies are introduced in the circuit if this property is not adequately treated. The proposed algorithm allows for the creation of other CAD tools, as for instance: a timing analysis tool, a generator of irredundant arithmetic circuits, or even a test generation tool, including list of faults, test vectors as well as fault coverage.