This dissertation studies a unique delta sigma modulator (DSM), known as reversed hysteresis delta sigma modulator (R-HDSM). This modulator is appropriate for ultra-high speed analog-to-digital converters, which can be used for communications and signal processing systems and their applications. Furthermore, the procedure to design the binary delta sigma modulator (BDSM) with a delay is developed and then parameters deltaOFF and deltaON ; are calculated for the system. In addition, analysis of the BDSM with a delay is achieved and the theoretical and simulated values compared. The reversed hysteresis delta sigma modulators are also analyzed, and the theoretical and the simulated values compared. The dissertation evaluates the performance measure for the suggested systems with continuous DSM and BDSM in terms of the spurious free dynamic range (SFDR), the signal to noise ratio (SNR), and the root mean square error (RMS). It studies the second-order R-HDSM. Finally, it compares the first-order R- HDSM and the second-order R-HDSM in terms of the signal to noise ratio (SNR).

In this research an approach to design and implement all-optical delta-sigma modulator (ODSM) has been expanded. The two main blocks of this modulator are “leaky integrator” and “bi-stable switch” designed and implemented by using active element like semiconductor optical amplifier (SOA) and other passive elements like optical filter, isolator and coupler. All experiments are done on optical table and proper results achieved. Thus the new bi-stable switch is designed and implemented by using “inverted bistable switch” and “non-inverted bi-stable switch”. This switch is made by five ring lasers. Right wavelengths have chosen for each ring laser to achieve a novel characteristic called “Proteresis”. All control parameters of this switch was investigated The major impact of this research will be in the area communication system, which need high resolution and fast modulation speed with less noise in their systems.

In this proposal, an advanced local oscillator with high resolution, low phase noise and fast switching characteristics is designed for wireless communication applications. The circuit is based on fractional-N frequency synthesis technique in which the use of delta-sigma modulator can remove the fractional spurs effectively. The mechanism in regard to fractional spurs and phase noise for a fractional-N frequency synthesizer will be studied and simulated by developing proper mathematical models. In the implementation of the local oscillator, the analog circuit includes a 1000-1033 MHz VCO, crystal oscillator and loop filter. The digital circuit includes a phase frequency detector, dual modulus divider and 3rd order delta-sigma modulator. At first a FPGA will be used to prototype the digital circuit. The final digital circuit will be implemented in a CMOS process and require 3V operation with low current consumption. The design specifications include that under 1 KHz resolution the phase noise levels are less than -90 dBc/Hz at frequency offets within a loop bandwidth more than 100 KHz. Spurious components are less than -90 dBc/Hz and switching time is less than 1 ms over a 30 MHz tuning range.

In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.

In the first, a time-variant modulus phase lock loop(PLL) model is established. Applying the model, Theorems of fractional-N synthesizers are introduced. We also explain theorems and simulations of Closed-Loop Modulation and Two-Point Delta Sigma Modulation with the model. In the end, a 2.4GHz FHSS transmitter using Two-Point Delta Sigma Modulation which meets Bluetooth specifications is demonstrated.

Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity. / text

In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.

In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.