This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

This dissertation is a contribution toward developing all-optical binary delta sigma modulator (BDSM) [‎27] by changing its bistability to proteretic bistability in order to increase the modulator bandwidth frequency. An innovative delta sigma modulator called proteretic binary delta sigma modulator (PBDSM), which is optically compatible, is investigated theoretically and by modeling and simulation and its bandwidth superiority is proven. The time interval of PBDSM Δt calculation is driven and dynamic performance measure of PBDSM comparing to previous related work is computed, modeled and simulated. Modeling and simulations are based on Matlab-Simulink for ideal environment testing. The basic components of BDSM are the leaky integrator and the bi-stable device. Thus, the focus was on improving the bi-stable device to overcome the bandwidth limitation toward THz modulation frequency in optical domain. Consequently, proteresis bistability was investigated in semi-practical domain, using Matlab-Simulink function, for clear realization of its input-output characteristics and compared with the corresponding hysteresis bistability. The contribution in this research, regarding proteresis bi-stable device design, can be implemented in current technologies, both optical and electrical, of continuous-time delta sigma modulation. Furthermore, the new design showed capability and more flexibility in manipulating its output form and it showed more control on the way of conducting delta sigma modulator error correction.

The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

This paper presents a distributed feedback and feedforward of discrete-time delta sigma modulator applications in the radio. We know the delta-sigma modulator using oversampling and noise shaping technique, thus we can relax the specifications of the components. This paper described the architectural differences and compare, the in-band signal is less sensitive to noise interference, and improve the resolution of the circuit. In the resonator, a simple structure with a small number of capacitor in resonator circuit. This paper uses the TSMC 0.18£gm process parameters to the simulation, implementation, and measurement. Our fourth-order discrete-time delta-sigma modulator specifications as follows: the input signal frequency is 10.7MHz, the sampling frequency is 42.8MHz, the signal bandwidth is 200kHz, oversampling rate is 107, and one bit quantizer.

This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

In this research an approach to all optical delta sigma modulator (ADSM) has been elaborated. Two important components of ADSM; "leaky integrator" and "inverted bi-stable quantizer" were modeled, on the basis of cross gain modulation of the Semiconductor Optical Amplifier (SOA). The simulations (via VPI photonics) were all in micrometer scale (suitable for chip fabrication). By simulating each element of ADSM the whole circuit was simulated and results have been showed and analyzed. By investigating the ADSM, the limiting factor for reaching higher frequencies (THz) was recognized to be the quantization device. Thus a new optical switch was introduced, for the first time so called "proteresis." By applying proteretic bi-stable device in the delta sigma modulator, the resonance frequency was improved minimum two fold from 295MHz to 575MHz without making any change in hysteretic bi-stable switch. The broad impact of this research is on the digital technologies that can be utilized in high-speed signal processing. The prime examples are the RF technologies used in military and civilian applications. Furthermore introduction of proteresis opens a new research gate for compensating delay in almost every system.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

Tato diplomová práce si klade za cíl seznámit čtenáře se základním konceptem a principy jednosmyčkových modulátorů . Diplomová práce ozřejmuje čtenáři problematiku delta-sigma () modulátorů s jednou zpětnovazební smyčkou. Zabývá se základními principy převzorkování u číslicově-analogových převodníků a rozšiřuje je o teorii tvarování spektra šumu. Vycházeje z této teorie jsou navrženy tři jednosmyčkové modulátory, které běží na 1024 OSR jako alternativa k běžně používáným modulátorům vysokých řádů. Modulátory jsou implementovány do FPGA společně s rekonstrukčním filtrem a podpůrnými bloky. Nakonec byl zkonstruován hardwarový prototyp pro vyhodnocení implementace navrženého DAC.