One of the objectives of this study is to develop a methodology, together with a set of software programs that evaluate, in a power system, the risks of catastrophic failures caused by hidden failures in the hardware or software components of the protection system. The disturbance propagation mechanism is revealed by the analysis of the 1977 New York Blackout. The step-by-step process of estimating the relay hidden failure probability is presented. A Dynamic Event Tree for the risk-based analysis of system catastrophic failures is proposed. A reduced 179-bus WSCC sample system is studied and the simulation results obtained from California sub-system are analyzed. System weak links are identified in the case study. The issues relating to the load and generation uncertainties for the risk assessment of system vulnerabilities are addressed. A prototype system - the Hidden Failure Monitoring and Control System (HFMCS) - is proposed to mitigate the risk of power system catastrophic failures. Three main functional modules - Hidden Failure Monitoring, Hidden Failure Control and Misoperation Tracking Database - and their designs are presented. Hidden Failure Monitoring provides the basis that allows further control actions to be initiated. Hidden Failure Control is realized by using Adaptive Dependability/Security Protection, which can effectively stop possible relay involvement from triggering or propagating disturbance under stressed system conditions. As an integrated part of the HFMCS, a Misoperation Tracking Database is proposed to track the performance of automatic station equipment, hence providing automatic management of misoperation records for hidden failure analysis. / Ph. D.

In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality.  The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.

Le domaine aéronautique connait de nos jours un engouement sans précédent autour de l’avion plus électrique. L’importance du nombre d’équipements électriques est à un tel point que l’amélioration de leur fiabilité devient incontournable. Actuellement, les composants passifs occupent 75 % des éléments électroniques utilisés en avionique dont la moitié correspond à des condensateurs. Ces derniers doivent donc répondre aux exigences environnementales avioniques assez contraignantes. C’est dans ce contexte que nous nous sommes intéressés particulièrement à l’étude des condensateurs à technologie film utilisant le polypropylène ou le polyester comme diélectrique. Afin de mieux comprendre le comportement fréquentiel de cette technologie, deux modèles fins de condensateurs films ont été développés, permettant ainsi de suivre les évolutions de leurs grandeurs électriques dans des conditions cohérentes avec l’application. Dans un deuxième temps, l’effet des contraintes en tension et en température constantes a été étudié sous la forme de facteurs d’accélération du vieillissement. Cela a été établi par l’intermédiaire de plusieurs essais, permettant d’établir les lois d’évolutions temporelles des paramètres électriques des condensateurs. Comme ces contraintes constantes ne sont pas toujours représentatives des conditions réelles d’utilisation, les cinétiques de dégradation ont été comparées à celles où les condensateurs sont sollicités par de fortes ondulations de courant, seules ou associées à une tension continue. Enfin, la dernière partie de notre travail expose l’utilisation des données expérimentales issues des essais de vieillissement dans un objectif de diagnostic en ligne. Les techniques utilisées assurent l'analyse de la dégradation de ces composants, étape essentielle dans la prédiction de l’état de santé des condensateurs en ligne / Nowadays, aeronautic research field is moving towards a more electric aircraft. Although this evolutionary path offers many advantages from a financial and ecological point of view, the increased power source usage sets additional constraints on the different electrical systems used onboard. Currently, passive components occupy 75% of the overall electronic equipments used in avionics, whose 50% corresponds to capacitors. Consequently, these latter must be able to withstand the harsh avionic operating conditions. In this thesis we were particularly interested in the study of metallized film capacitors technology using polyester or polypropylene as dielectric. A first approach consisted on the modeling of these components as function of frequency in order to study the evolution of their electrical parameters under consistent avionic stresses. These models were also developed on the purpose of tracking the degradation of the capacitors parameters over time. This operation was done by the means of accelerated floating ageing tests, where capacitors were subjected to different constant voltages and temperatures. Original capacitance ageing laws were thus proposed based on the identification of voltage and temperature degradation kinetics. However, since traditional floating ageing tests, do not reflects the normal ageing of the component, degradation kinetics of metallized films capacitors under high ripple currents, alone or combined with a DC voltage across the devices terminals where also studied, and the associated failure mechanisms were identified. A final step consisted on the health monitoring of metallized film capacitors online based on the experimental ageing data

Este trabalho propõe diretrizes de Gestão de Continuidade de Negócios (GCN) para a tecnologia de Ensino Presencial Mediado por Recursos Tecnológicos (EPMRT), que conta, para a realização de suas atividades acadêmicas, com um sistema complexo para transmissão de aulas e exige um grande esforço para o controle das suas operações e das respostas coordenadas diante de erros, falhas e defeitos, ou quaisquer incidentes que resultem na interrupção das suas atividades. A manutenção deste ambiente tecnológico está relacionada com a implantação de processos eficientes de gestão de risco e do ciclo de melhoria contínua em ambiente de TI com a adoção do ITIL® e através da construção das diretrizes de um Plano de Continuidade de Negócios (PCN), documentado por meio de elementos da UML, utilizando a Análise de Impacto nos Negócios (BIA), a Avaliação dos Riscos (RA) e os atributos de Dependabilidade para os elementos tecnológicos: disponibilidade, confiabilidade, segurança, confidencialidade, integridade e manutenibilidade. / This paper proposes guidelines for Business Continuity Management (BCM) that uses a technology called Education System Mediated Classroom Resources Technology (SPMRT), which needs, for the achievement of their academic activities, a complex system for transmission of lessons and requires a great effort to control their operations and coordinated fast responses in case of errors, faults, attacks and defects, or any incidents that result in the disruption of their activities. Maintaining this technological environment is related to the implementation of efficient processes of risk management and continuous improvement cycle in the IT environment with the adoption of ITIL® and through the construction of a Business Continuity Plan (BCP), documented by elements of the UML using the Business Impact Analysis (BIA), Risk Assessment (RA) and the attributes of Dependability: availability, reliability, security, confidentiality, integrity and maintainability.

Les études de Sûreté de Fonctionnement (SdF) sur les barrières instrumentées de sécurité représentent un enjeu important dans de nombreux domaines industriels. Afin de pouvoir réaliser ce type d'études, TOTAL développe depuis les années 80 le logiciel GRIF. Pour prendre en compte la complexité croissante du contexte opératoire de ses équipements de sécurité, TOTAL est de plus en plus fréquemment amené à utiliser le moteur de calcul MOCA-RP du package Simulation. MOCA-RP permet d'analyser grâce à la simulation de Monte-Carlo (MC) les performances d'équipements complexes modélisés à l'aide de Réseaux de Petri (RP). Néanmoins, obtenir des estimateurs précis avec MC sur des équipements très fiables, tels que l'indisponibilité, revient à faire de la simulation d'événements rares, ce qui peut s'avérer être coûteux en temps de calcul. Les méthodes standard d'accélération de la simulation de Monte-Carlo, initialement développées pour répondre à cette problématique, ne semblent pas adaptées à notre contexte. La majorité d'entre elles ont été définies pour améliorer l'estimation de la défiabilité et/ou pour les processus de Markov. Par conséquent, le travail accompli dans cette thèse se rapporte au développement de méthodes d'accélération de MC adaptées à la problématique des études de sécurité se modélisant en RP et estimant notamment l'indisponibilité. D'une part, nous proposons l'Extension de la Méthode de Conditionnement Temporel visant à accélérer la défaillance individuelle des composants. D'autre part, la méthode de Dissociation ainsi que la méthode de ``Truncated Fixed Effort'' ont été introduites pour accroitre l'occurrence de leurs défaillances simultanées. Ensuite, nous combinons la première technique avec les deux autres, et nous les associons à la méthode de Quasi-Monte-Carlo randomisée. Au travers de diverses études de sensibilité et expériences numériques, nous évaluons leur performance, et observons une amélioration significative des résultats par rapport à MC. Par ailleurs, nous discutons d'un sujet peu familier à la SdF, à savoir le choix de la méthode à utiliser pour déterminer les intervalles de confiance dans le cas de la simulation d'événements rares. Enfin, nous illustrons la faisabilité et le potentiel de nos méthodes sur la base d'une application à un cas industriel. / The dependability analysis of safety instrumented systems is an important industrial concern. To be able to carry out such safety studies, TOTAL develops since the eighties the dependability software GRIF. To take into account the increasing complexity of the operating context of its safety equipment, TOTAL is more frequently led to use the engine MOCA-RP of the GRIF Simulation package. Indeed, MOCA-RP allows to estimate quantities associated with complex aging systems modeled in Petri nets thanks to the standard Monte Carlo (MC) simulation. Nevertheless, deriving accurate estimators, such as the system unavailability, on very reliable systems involves rare event simulation, which requires very long computing times with MC. In order to address this issue, the common fast Monte Carlo methods do not seem to be appropriate. Many of them are originally defined to improve only the estimate of the unreliability and/or well-suited for Markovian processes. Therefore, the work accomplished in this thesis pertains to the development of acceleration methods adapted to the problematic of performing safety studies modeled in Petri nets and estimating in particular the unavailability. More specifically, we propose the Extension of the "Méthode de Conditionnement Temporel" to accelerate the individual failure of the components, and we introduce the Dissociation Method as well as the Truncated Fixed Effort Method to increase the occurrence of their simultaneous failures. Then, we combine the first technique with the two other ones, and we also associate them with the Randomized Quasi-Monte Carlo method. Through different sensitivities studies and benchmark experiments, we assess the performance of the acceleration methods and observe a significant improvement of the results compared with MC. Furthermore, we discuss the choice of the confidence interval method to be used when considering rare event simulation, which is an unfamiliar topic in the field of dependability. Last, an application to an industrial case permits the illustration of the potential of our solution methodology.

Este trabalho propõe diretrizes de Gestão de Continuidade de Negócios (GCN) para a tecnologia de Ensino Presencial Mediado por Recursos Tecnológicos (EPMRT), que conta, para a realização de suas atividades acadêmicas, com um sistema complexo para transmissão de aulas e exige um grande esforço para o controle das suas operações e das respostas coordenadas diante de erros, falhas e defeitos, ou quaisquer incidentes que resultem na interrupção das suas atividades. A manutenção deste ambiente tecnológico está relacionada com a implantação de processos eficientes de gestão de risco e do ciclo de melhoria contínua em ambiente de TI com a adoção do ITIL® e através da construção das diretrizes de um Plano de Continuidade de Negócios (PCN), documentado por meio de elementos da UML, utilizando a Análise de Impacto nos Negócios (BIA), a Avaliação dos Riscos (RA) e os atributos de Dependabilidade para os elementos tecnológicos: disponibilidade, confiabilidade, segurança, confidencialidade, integridade e manutenibilidade. / This paper proposes guidelines for Business Continuity Management (BCM) that uses a technology called Education System Mediated Classroom Resources Technology (SPMRT), which needs, for the achievement of their academic activities, a complex system for transmission of lessons and requires a great effort to control their operations and coordinated fast responses in case of errors, faults, attacks and defects, or any incidents that result in the disruption of their activities. Maintaining this technological environment is related to the implementation of efficient processes of risk management and continuous improvement cycle in the IT environment with the adoption of ITIL® and through the construction of a Business Continuity Plan (BCP), documented by elements of the UML using the Business Impact Analysis (BIA), Risk Assessment (RA) and the attributes of Dependability: availability, reliability, security, confidentiality, integrity and maintainability.

En la presente tesis se propone una metodología de desarrollo de estrategias híbridas para la mitigación de fallos inducidos por radiación en los sistemas empotrados modernos. La propuesta se basa en los principios del co-diseño de sistemas y consiste en la combinación selectiva, incremental y flexible de enfoques de tolerancia a fallos basados en hardware y software. Es decir, la exploración del espacio de soluciones se fundamenta en una estrategia híbrida de grano fino. El flujo de diseño está guiado por los requisitos de la aplicación. Esta metodología se ha denominado: co-endurecimiento. De esta forma, es posible diseñar sistemas embebidos confiables a bajo coste, donde no sólo se satisfagan los requisitos de confiabilidad y las restricciones de diseño, sino que también se evite el uso excesivo de costosos mecanismos de protección (hardware y software).

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.