Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 322-323)

Techn. Hochsch., Diss. u.d.T.: Hoffmann, Andreas: A methodology for the efficient design of application-specific instruction-set processors using the machine description language LISA--Aachen, 2002.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 61). Also available online.

Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "March 2006." Includes bibliographical references (p. 145-151). Also available via the World Wide Web.

Orientadores: Sandro Rigo, Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-19T17:27:58Z (GMT). No. of bitstreams: 1 Garcia_MaxiwellSalvador_M.pdf: 2001408 bytes, checksum: 18a0b7e502a8676d32857b27374a5d77 (MD5) Previous issue date: 2011 / Resumo: O simulador é uma das ferramentas mais importantes para o desenvolvimento de uma nova arquitetura computacional. Entre as vantagens que ele apresenta destacam-se a flexibilidade e o baixo custo. Os primeiros simuladores eram criados manualmente, uma prática muito propensa a erros. Atualmente, Linguagens de Descrição de Arquiteturas (ADLs) facilitam a geração dessas ferramentas. O foco deste trabalho é a pesquisa em técnicas de simulação rápida utilizando a ADL ArchC. Partindo do estado da arte nesta área, a simulação compilada, conseguiu-se melhorar ainda mais o desempenho dos simuladores de conjunto de instruções. Duas abordagens compilada foram usadas. A primeira é uma abordagem estática, que analisa e decodifica o binário previamente e especializa o simulador para aquela aplicação, deixando a simulação com um alto desempenho. As simulações ficaram apenas 5 vezes mais lentas, na média, que execuções nativas em máquina Intel, com desempenho atingindo 900 milhões de instruções por segundo. A segunda abordagem é a dinâmica, que não exige o conhecimento prévio da aplicação, evitando a sobrecarga inicial de se especializar o simulador. Com essa abordagem é possível, também, simular aplicativos que sofrem modificações em seu próprio código, como boot-loader e sistemas operacionais. A decodificação e compilação do aplicativo são feitas em tempo de execução, fazendo uso da infraestrutura LLVM. O desempenho de simulação só não superou o estático, alcançando uma média de 140 milhões de instruções por segundo. Considerando-se a sobrecarga de geração do simulador compilado estático, a abordagem dinâmica torna-se mais rápida, mostrando-se uma excelente alternativa ao projetista que não tem o interesse em ficar simulando repetidas vezes a mesma aplicação / Abstract: The simulator is one of the most important tools to design a new computer architecture. It has many advantages, the most important are exibility and low cost. The _rst simulators were written from scratch, which was an error-prone practice. Nowadays, Architecture Description Languages (ADLs) simplify the generation of these tools. This work focus on the research of new fast simulation techniques using the ArchC ADL. Beginning from the state-of-art in this area, the compiled simulation, is was possible to speed-up the instruction set simulation performance even higher. Two approaches have been used. The _rst is static compiled simulation, which analyzes and decodes the binary, and specializes the simulator for that application, improving the simulation and reaching high performance. The simulations were only 5 times slower, on average, if compared to native execution on an Intel machine, reaching 900 million instructions per second. The second approach is a dynamic compiled simulation, which requires no knowledge about the application, avoiding the overhead of specializing the simulator. With this approach it is possible to simulate sef-modifying code, such as in boot-loaders and operating systems. The application is decoded and compiled at runtime, using the LLVM framework. The simulation performance reaches an average of 140 million instructions per second, not overcoming the static approach. However, if you consider the overhead of generating the static compiled simulator, the dynamic approach becomes better, being an excellent alternative to the designer who has no interest in repeating simulations for the same application / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

Context: Over the last two decades, software architecture has introduced a new trend insoftware development. This new trend has completely changed the normal methods andpractices of software engineering. The focus has become the architectural elements ratherthan code and sub-routines. Architecture description languages (ADLs) have been proposedfor this kind of architecture based software development. There are a number of differentADLs both in academia and industry; they are not totally adopted by the software engineeringcommunity, but they are not avoided either. In this research work, an investigation has beenperformed based on the ADLs evaluation in practice. Objectives: The main aim of this study is to investigate evaluation of ADLs in academia andindustry. To explore the benefits and drawbacks of ADLs in practice. The study also exploresthe different quality factors improved by ADLs. Further different methods used to buildarchitecture with ADLs and then how to use architecture described with an ADL in softwaredevelopment and maintenance have also been reported. Methods: This research study has been carried out using the systematic literature reviewmethod. The systematic literature review follows the guidelines suggested by Kitchenham[21]. Results: This research review has resulted in total of 102 different ADLs. It has been foundthat out of the 102 different ADLs, 69 ADLs have been evaluated in academia and only 33ADLs have been evaluated in industry. ADLs have also been classified based on theirindustrial and academia evaluation. There are total 31 different benefits and 19 differentdrawbacks of ADLs have been identified. This review also extracted 20 different qualityfactors from literature that are improved by using ADLs in practice. Further 13 differentmethods used to build architecture with ADL have also been reported. Finally 9 differentmethods of ADLs used in software development and maintenance have been identified. Conclusions: The Large number of ADLs with little evaluation in industry suggests thatmore work needs to be done in order to improve ADLs evaluation in practice. ADLs providemore benefits compared to their drawbacks which suggests that ADLs can be very beneficial.Knowledge gained during this research study, suggests that ADLs are mostly unrecognized.More awareness about ADLs should be provided in education and practice.

Les architectures logicielles ont un rôle important dans le développement de systèmes à logiciel prépondérant afin de permettre la satisfaction tant des exigences fonctionnelles que des exigences extra-fonctionnelles. En particulier, les architectures logicielles dynamiques ont émergé pour faire face aux caractéristiques des systèmes contemporains qui opèrent dans des environnements dynamiques et par conséquent susceptibles de changer en temps d’exécution. Les langages de description architecturale (ADLs) sont utilisés pour représenter les architectures logicielles en produisant des modèles qui peuvent être utilisés pendant la conception ainsi que l’exécution. Cependant, la plupart des ADLs existants sont limités sur plusieurs facettes : (i) ils ne décrivent que les aspects structurels, topologiques de l’architecture ; (ii) ils ne fournissent pas un support adéquat pour représenter les aspects comportementaux de l’architecture ; (iii) ils ne permettent pas de décrire des aspects avancés de la dynamique de l’architecture ; (iv) ils sont limités en ce qui concerne la vérification automatisée des propriétés et des contraintes architecturales ; et (v) ils sont déconnectés du niveau d’implémentation et entraînent souvent des incohérences entre l’architecture et l’implémentation. Pour faire face à ces problèmes, cette thèse propose un framework formel pour les architectures logicielles dynamiques. Ce framework comprend : (i) .-ADL, un langage formel pour décrire des architectures logicielles dynamiques sous les perspectives structurelles et comportementales ; (ii) la spécification des opérations de reconfiguration dynamique programmée ; (iii) la génération automatique de code source à partir des descriptions architecturales ; et (iv) une approche basée sur la vérification statistique pour exprimer et vérifier formellement des propriétés des architectures logicielles dynamiques. Les contributions principales apportées par le framework proposé sont quatre. Premièrement, le langage .-ADL a été doté de primitives de niveau architectural pour décrire des reconfigurations dynamiques programmées. Deuxièmement, les descriptions architecturales dans .-ADL sont transformées vers le code source d’implémentation dans le langage de programmation Go, en contribuant à minimiser les dérives architecturales. Troisièmement, une nouvelle logique appelée DynBLTL est utilisée pour exprimer formellement des propriétés dans les architectures logicielles dynamiques. Quatrièmement, un outil basé sur SMC a été développé pour automatiser la vérification des propriétés architecturales en cherchant à réduire l’effort, les ressources computationnelles, et le temps pour réaliser cette tâche. Dans ce travail, deux systèmes basés sur réseaux de capteurs sans fil sont utilisés pour valider les éléments du framework. / Software architectures play a significant role in the development of software-intensive systems in order to allow satisfying both functional and non-functional requirements. In particular, dynamic software architectures have emerged to address characteristics of the contemporary systems that operate on dynamic environments and consequently subjected to changes at runtime. Architecture description languages (ADLs) are used to represent software architectures, producing models that can be used at design time and/or runtime. However, most existing ADLs have limitations in several facets: (i) they are focused on structural, topological aspects of the architecture; (ii) they do not provide an adequate support for representing behavioral aspects of the architecture; (iii) they do not allow describing advanced aspects regarding the dynamics of the architecture; (iv) they are limited with respect to the automated verification of architectural properties and constraints; and (v) they are disconnected from the implementation level, thus entailing inconsistencies between architecture and implementation. In order to tackle these problems, this thesis proposes formally founded framework for dynamic software architectures. Such a framework comprises: (i) .-ADL, a formal language for describing software architectures under both structural and behavioral viewpoints; (ii) the specification of programmed dynamic reconfiguration operations; (iii) the automated generation of source code from architecture descriptions; and (iv) an approach based on statistical model checking (SMC) to formally express and verify properties in dynamic software architectures. The main contributions brought by the proposed framework are fourfold. First, the .-ADL language was endowed with architectural-level primitives for describing programmed dynamic reconfigurations. Second, architecture descriptions in .-ADL are translated towards implementation source code in the Go programming language, thereby contributing to minimize architectural drifts. Third, a novel logic, called DynBLTL, is used to formally express properties in dynamic software architectures. Fourth, a toolchain relying on SMC was built to automate the verification of architectural properties while striving to reduce effort, computational resources, and time for performing such a task. In this work, two wireless sensor network-based systems are used to validate the framework elements.

The invention of Hardware Description Languages has given hardware designers access to powerful methods of abstraction and organization, previously only available to software developers. A high-powered means of examining properties such as reliability, correctness and safety is the creation of formal, mathematical proofs of correctness. One approach to this is the modelling of the artifact in the logic of some deductive system, such as the higher order logic of the Prototype Verification System (PVS). The ambition of this work is to demonstrate a mechanism by which a class of hardware descriptions may be used to generate such models automatically. We further demonstrate the utility of said models, using them to demonstrate non-trivial correctness properties. We also present a method of generating hardware descriptions, logical models, and proofs from a class of tabular specifications. The language on which this method operates is Bluespec SystemVerilog (BSV), a high-level hardware description language notable for its elegant semantics. The target platform of our translation is the Prototype Verification System (PVS), which features a highly automatic theorem-proving system. The translation algorithm is discussed at length, including the reconciliation of BSV's action-oriented semantic and the Kripke semantics employed by our chosen model in PVS. Five case studies demonstrate our methodology. In studies one and two, function blocks of the IEC 61131-3 Annex F library are verified against tabular specifications, or generated from the same. The remaining case studies are based on the Shakti RISC-V implementation of the RapidIO subsystem. Our final case study demonstrates progress towards the verification of highly abstract and complex properties over the entire translatable subset of the RapidIO library. / Thesis / Doctor of Philosophy (PhD) / The invention of Hardware Description Languages has given hardware designers access to powerful methods of abstraction and organization, previously only available to software developers. A high-powered means of examining properties such as reliability, correctness and safety is the creation of formal, mathematical proofs of correctness. One approach to this is the modelling of the artifact in the logic of some deductive system, such as the higher order logic of the Prototype Verification System (PVS). The ambition of this work is to demonstrate a mechanism by which a class of hardware descriptions may be used to generate such models automatically. We further demonstrate the utility of said models, using them to demonstrate non-trivial correctness properties. We also present a method of generating hardware descriptions, logical models, and proofs from a class of tabular specifications. The language on which this method operates is Bluespec SystemVerilog (BSV), a high-level hardware description language notable for its elegant semantics. The target platform of our translation is the Prototype Verification System (PVS), which features a highly automatic theorem-proving system. The translation algorithm is discussed at length, including the reconciliation of BSV's action-oriented semantic and the Kripke semantics employed by our chosen model in PVS. Five case studies demonstrate our methodology. In studies one and two, function blocks of the IEC 61131-3 Annex F library are verified against tabular specifications, or generated from the same. The remaining case studies are based on the Shakti RISC-V implementation of the RapidIO subsystem. Our final case study demonstrates progress towards the verification of highly abstract and complex properties over the entire translatable subset of the RapidIO library.

This thesis is one of the first to introduce a systematic and general Source Language Analysis System (called SLA) for a high -level synthesis system.

The Internet is a vastly under-utilised resource, only used for half of the IT story. Describe the Internet in two words and many might say ‘sharing knowledge’. But sharing information is more accurate. It’s just that all the principle ways we use the Internet — the Web, email and media streaming — happen to be examples where information is in the form of knowledge. But IT — Information Technology — has another side: the realm of software programming where information means the dynamic control of how things work. The Internet is the driving force in the IT industry, so why isn’t it also known for sharing control? True, there are examples of specialised, one-off software applications interfacing with each other via the Internet, but there has yet to be any systematic and universal attempt to exploit the potential of the Internet for control-IT in the way we have seen it for knowledge-IT. Taking the strengths of the Web model as a starting point, this thesis proposes a parallel, dynamic world to the Web called The Mesh. In the same way that the Web seamlessly connects databases of the world to provide a global font of knowledge, the Mesh would connect software of the world to provide a global means of control. The Mesh would embody all the successful, empowering features of the Web. Everyone would have a say in how things work, mirroring Web 2.0’s user-generated content but for software instead of media. In being a universally integrated design approach for device control, the Mesh would encompass a number of research areas working on the control issue at the big picture level. It would address the problems of universal usability and ubiquitous computing. It would also provide solutions in agent-based systems and grid computing. But many features of the Mesh would simply be unique. They would change the way we go about software design, leading to new opportunities for users, programmers and manufacturers alike. The key to everything is design simplicity. A concept demonstrator has been developed as an integral part of this research project. It shows that the Mesh is both feasible and practical. Examples of programs run in the concept demonstrator are discussed, showing exactly how the Mesh would be built and how it would work. / Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2007