Light emitting transistors (LETs) and transistor lasers (TLs) are newly-emerging optoelectronic devices capable of emitting spontaneous or stimulated light while performing transistor actions. This dissertation describes the design, growth, and performances of long wavelength LETs and TLs based on InAlGaAs/InP material system. First, the doping behaviors of zinc (Zn) and carbon (C) in InAlGaAs layers for p-type doping were investigated. Using both dopants, the N-InP/p-In0.52(AlxGa1-x)0.48As/N-In0.52Al0.48As LETs with InGaAs quantum wells (QWs) in the base demonstrate both light emission and current gains (β). The device performances of Zn- and C-doped LETs have been compared, which is explained by a charge control analysis involving the quantum capture and recombination process in the QWs. A TL based on a C-doped double heterostructure (DH-TL) with single QW was designed and fabricated. The device lases at 77 K with a threshold current density (Jth) of 2.25 kA/cm2, emission wavelength (λ) at ~1.55 µm, and β of 0.02. The strong intervalence band absorption (IVBA) is considered as the main intrinsic optical loss that prohibits the device from lasing at room temperature. Based on a threshold condition analysis taking into account the strong IVBA, it is found that room-temperature lasing of a DH-TL is achieved only when the base thickness and doping level are within a specific narrow range and improved performance is expected in a separate confinement heterostructure (SCH) TL.

It has been predicted that gold, aluminum, and copper do not fundamentally change the graphene band structure when they are in close proximity to graphene, but merely increase the doping. My data confirms this prediction, as well as explores other consequences of the metal/graphene interface. First, I present a technique to fabricate thin oxide barriers between graphene and aluminum and copper to create tunnel junctions and directly probe graphene in close proximity to a metal. I map the differential conductance of the junctions versus tunnel probe and back gate voltage, and observe mesoscopic fluctuations in the conductance that are directly related to the graphene density of states. I develop a simple theory of tunneling into graphene to extract experimental numbers, such as the doping level of the graphene, and take into account the electrostatic gating of graphene by the tunneling probe. Next, results of measurements in magnetic fields will also be discussed, including evidence for incompressible states in the Quantum Hall regime wherein an electron is forced to tunnel between a localized state and an extended state that is connected to the lead. The physics of this system is similar to that encountered in Single Electron Transistors, and some work in this area will be reviewed. Finally, another possible method of understanding the interface between a metal and graphene through transport is presented. By depositing disconnected gold islands on graphene, I am able to measure resonances in the bias dependent differential resistance, that I connect to interactions between the graphene and gold islands.

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La réduction des dimensions des dispositifs MOSFET devient de plus en plus complexe a réalisé, et les nouvelles technologies MOSFET se confrontent à de fortes difficultés. Pour surmonter ce problème, une nouvelle technique, appelée intégration 3D VLSI, est étudiée : remplacer la structure plane conventionnelle par un empilement vertical de transistors.En particulier, l’intégration 3D séquentielle ou CoolCube™ au CEA-Leti permet de profiter pleinement de la troisième dimension en fabriquant séquentiellement les transistors. La réalisation d’une telle intégration apporte une nouvelle contrainte, celle de fabriquer le transistor du dessus avec un budget thermique faible (inférieur à 500°C), afin de préserver les performances du transistor d'en dessous. Puisque ce budget thermique est principalement influencé par l'activation des dopants, plusieurs techniques innovatrices sont actuellement investiguées au CEA-LETI, afin de fabriquer le drain et la source. Dans ce manuscrit, nous utiliserons la recristallisation en phase solide comme mécanisme pour activer les dopants (inférieures à 600 °C). L’objectif de cette thèse est donc de fabriquer et de caractériser des transistors dont l’activation des dopants est réalisée grâce à ce mécanisme, afin d’atteindre des performances similaires à des transistors réalisés avec un budget thermique standard. Ce travail est organisé autour de l’activation des dopants, et en trois chapitres, où chaque chapitre est spécifique à une intégration (« Extension Last »/ « Extension First », « Gate Last »/ « Gate First ») et à une architecture (FDSOI, FINFET) considérées. Ces chapitre permettront, grâce aux caractérisations électriques, morphologiques et aux simulations, de développer un procédé de recristallisation stable à 500°C, à la fois pour les nMOS et les pMOS, et de proposer de nouveaux schémas d’intégrations, afin de réaliser des transistors à faible budget thermique et compatibles avec l’intégration 3D Séquentielle. / The down scaling of MOSFET device is becoming harder and the development of future generation of MOSFET technology is facing some strong difficulties. To overcome this issue, the vertical stacking of MOSFET in replacement of the conventional planar structure is currently investigated. This technique, called 3D VLSI integration, attracts a lot of attention, in research and in the industry. Indeed, this sequential stacking of transistor enables to gain in density and performance without reducing transistors dimensions.More specifically, 3D sequential integration or CoolCube™ at CEA-Leti enables to fully benefit of the third dimension by sequentially manufacturing transistors. Implementing such an integration provides the new constraint of manufacturing top transistor with low thermal budget (below 500°C) in order to preserve bottom-transistor performances. As most of the thermal budget is due to the dopant activation, several innovative techniques are currently investigated at CEA-LETI.In this work, solid phase epitaxy regrowth will be used as the mechanism to activate dopants below 600°C. The aim of this thesis is thus to manufacture and to characterize transistors with low-temperature dopant activation, in order to reach the same performance as devices manufactured with standard thermal budget. The work is organized around the dopant activation, and in three chapters, according to each considered integration scheme (Extension Last/ Extension First, Gate Last/ Gate First) and architecture (FDSOI, FINFET). These chapters, assisted by relevant simulations, electrical and morphological characterizations, will enable to develop a new and stable 500°C recrystallization process for both N and P FETs, and to propose new integration schemes in order to manufacture transistors with low thermal budget and compatible with the 3D sequential integration.

This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags. OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.

This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags. OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.

<div>With the transistor dimensions scaling down to a few atoms, quantum phenomena - like quantum tunneling and entanglement - will dictate the operation and performance of the next generation of electronic devices, post-CMOS era. While quantum tunneling limits the scaling of the conventional transistor, Tunneling Field Effect Transistor (TFET) employs band-to-band tunneling for the device operation. This mechanism can reduce the sub-threshold swing (S.S.) beyond the Boltzmann's limit, which is fundamentally limited to 60 mV/dec in a conventional Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). A smaller S.S. ensures TFET operation at a lower supply voltage and, therefore, at lesser power compared to the conventional Si-based MOSFET.</div><div><br></div><div>However, the low transmission probability of the band-to-band tunneling mechanism limits the ON-current of a TFET. This can be improved by reducing the body thickness of the devices i.e., using 2-Dimensional (2D) materials or by utilizing heterojunction designs. In this thesis, two promising methods are proposed to increase the ON-current; one for the 2D material TFETs, and another for the III-V heterojunction TFETs.</div><div><br></div><div>Maximizing the ON-current in a 2D material TFET by determining an optimum channel thickness, using compact models, is presented. A compact model is derived from rigorous atomistic quantum transport simulations. A new doping profile is proposed for the III-V triple heterojunction TFET to achieve a high ON-current. The optimized ON-current is 325 uA/um at a supply voltage of 0.3 V. The device design is optimized by atomistic quantum transport simulations for a body thickness of 12 nm, which is experimentally feasible.</div><div> </div><div>However, increasing the device's body thickness increases the atomistic quantum transport simulation time. The simulation of a device with a body thickness of over 12 nm is computationally intensive. Therefore, approximate methods like the mode-space approach are employed to reduce the simulation time. In this thesis, the development of the mode-space approximation in modeling the triple heterojunction TFET is also documented.</div><div><br></div><div>In addition to the TFETs, quantum computing is an emerging field that utilizes quantum phenomena to facilitate information processing. An extra chapter is devoted to the electronic structure calculations of the Si:P delta-doped layer, using the empirical tight-binding method. The calculations agree with angle-resolved photoemission spectroscopy (ARPES) measurements. The Si:P delta-doped layer is extensively used as contacts in the Phosphorus donor-based quantum computing systems. Understanding its electronic structure paves the way towards the scaling of Phosphorus donor-based quantum computing devices in the future.</div>

III-Nitride semiconductor materials have garnered significant attention among researchers due to their diverse applications stemming from their remarkable electrical and optical properties. This present thesis encompasses theoretical investigations conducted on InAlN and AlGaN for the purpose of designing light-emitting diodes (LEDs), along with experimental characterization experiments on BGaN thin films. The primary objective of this research is to delve deeply into the optoelectronic applications of InAlN and analyze the current state of BGaN. Theoretical studies were carried out on InAlN-based deep-ultraviolet (DUV) LEDs, with a particular focus on elucidating the polarization properties exhibited by this material when combined with AlGaN. Additionally, an estimation of the band alignment of this system was included, taking into account the available reported data. The intention behind this work is to underscore the importance of designing novel optoelectronic devices that incorporate ternary-to-ternary heterointerfaces. However, it is crucial to carefully consider both the advantages and disadvantages of such interfaces in terms of carrier injection efficiency and radiative efficiency. The experimental section of this thesis entailed the fabrication and characterization of BGaN thin films. A comprehensive understanding and development of this material are essential, as boron-alloys have garnered attention due to their unique properties. Nevertheless, there have been reports of epitaxial complications and theoretical limits associated with these alloys. In this section, we present the characteristics of the first conductive memory-effect-obtained p-type BGaN, doped with magnesium. Although the characterization of the reported samples includes techniques such as HRXRD, AFM, SEM, Hall, CTLM, SIMS, and CL, it is important to note that a more profound fundamental study is still underway. The relevance of this work can be summarized into two key aspects: Firstly, it provides valuable insights and descriptions of novel heterojunctions for ultraviolet LEDs from a physics perspective. Secondly, it contributes to material advancements in the pursuit of developing new ternary-alloys, offering a material science perspective.