During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.

The transition from the 5G to the 6G era is a pivotal juncture in contemporary wireless communication. Under such a circumstance, Digital Pre-Distortion (DPD) technology has established its significance as an effective method to linearize Power Amplifiers. However, DPD is facing a series of challenges, notably the increased bandwidth which necessitates more complex modeling techniques. This thesis focuses on the fact that the DPD requires multi-ported memories for the Look-Up-Tables to store correction coefficients, where two research questions are identified. Firstly, this thesis analyses the power, area, and delay-performance trade-offs with an increase in the number of read and write ports of Flip-Flop (FF)-based memories. Secondly, this thesis evaluates and compares the performance of the conventional FF-based multi-ported memories and algorithmic FF-based multi-ported memories. As a Master’s thesis project, this research utilizes the knowledge and practice skills expected of a Master’s student specializing in Embedded Systems. In this thesis, conventional and algorithmic multi-ported memories are implemented and evaluated after studying related works. Subsequently, an industrial Application-Specific Integrated Circuit (ASIC) design flow is executed, undergoing iterative refinements. And in the end, the conclusions are drawn based on an analysis of the software reports. The results underscore that area and power consumption exhibit linear growth alongside increased port numbers within conventional multi-ported memories. Also, the algorithmic multi-ported memory presents a promising alternative, engendering improvements across all three dimensions of delay, area, and power consumption. The implemented memories can be integrated into DPD forward path with customized port numbers in the future, offering adaptability in terms of port configuration and better performance in terms of timing, area and power. Additionally, these implemented memories stand as a valuable point of reference for engineers engaged in the development of FF-based multi-ported memories within the context of ASIC. / Övergången från den 5G- till den 6G- eran är en avgörande tidpunkt inom samtida trådlös kommunikation. Under sådana omständigheter har DPDtekniken etablerat sin betydelse som en effektiv metod för att linjärisera effektförstärkare. Dock står DPD inför en rad utmaningar, särskilt den ökade bandbredden som kräver mer komplexa modelleringstekniker. Denna avhandling fokuserar på det faktum att DPD kräver flerportsminnen för att Look-Up-Tables ska lagra korrigeringskoefficienter, där två forskningsfrågor identifieras. För det första analyserar denna avhandling effekt- , area- och fördröjningsprestanda-avvägningar med en ökning av antalet läs- och skrivportar för FF-baserade minnen. För det andra utvärderar och jämför denna avhandling prestandan hos konventionella FF-baserade multiportade minnen och algoritmiska FF-baserade multiportade minnen. Som ett masteruppsatsprojekt använder denna forskning de kunskaper och övningsfärdigheter som förväntas av en masterstudent som specialiserar sig på inbyggda system. I denna avhandling implementeras och utvärderas konventionella och algoritmiska flerportade minnen efter att ha studerat relaterade arbeten. Nästa steg är att genomföra en industriell ASIC-designflöde som genomgår iterativa förbättringar. Och till slut dras slutsatserna baserat på en analys av mjukvarurapporterna. Denna avhandling understryker att area och strömförbrukning ökar linjärt med ökade portnummer inom konventionella flerportade minnen. Å andra sidan presenterar det algoritmiska flerportade minnet ett lovande alternativ och ger förbättringar inom alla tre dimensioner av fördröjning, area och strömförbrukning. De implementerade minnena kan integreras i DPD-signalförloppet med anpassade portnummer i framtiden och erbjuda anpassningsbarhet när det gäller portkonfiguration och bättre prestanda vad gäller tid, area och ström. Dessutom utgör dessa implementerade minnen en värdefull referenspunkt för ingenjörer som är engagerade i utvecklingen av FF-baserade flerportade minnen inom ramen för ASIC.

Yes / RF power amplifiers in mobile WiMAX transceivers operate in an inherently nonlinear manner. It is possible to amplify the signal in the linear region, and avoid distortion, using output power back-off; however, this approach may suffer significant reduction in efficiency and power output. This paper investigates the use of Doherty techniques instead of back-off, to simultaneously achieve good efficiency and acceptable linearity. A 3.5 GHz Doherty RFPA has been designed and optimized using a large signal model simulation of the active device, and performance analysis under different drive levels. However, the Doherty EVM is generally poor for mobile WiMAX. Linearity may be improved by further digital pre-distortion, and a simple pre-distortion method using forward and reverse AM-AM and AM-PM modeling. Measurements on the realized amplifier show that this approach satisfies the EVM requirements for WiMAX base stations. It exhibits a PAE over 60%, and increases the maximum linear output power to 43 dBm, whilst improving the EVM.

Application Specific Integrated Circuits (ASICs) are critical to delivering on 5G’s promises of high speed, low latency, and expanded capacity. Digital Front-End (DFE) ASICs are particularly important components because they enhance crucial signal processing activities. It handles duties including carrier mixing, up-sampling, and modulation-demodulation, allowing for efficient data transmission and reception inthe complicated 5G environment. The main aim of this work is to develop a power estimation tool for DFE radio ASICs and to understand the different use cases. It also studies the spread of power consumption, taking into account process and metal variations. The thesis provides a detailed case study of the DFE ASIC, including its Intellectual Property (IP) blocks, configurations, and protocols. It investigates the power consumption of DFE ASICs under various conditions, including active processing, power-saving mode, and no clock. In this thesis we build a power model that describes how the factors affect the ASIC’s power consumption. It also performs spread analysis to evaluate the impact of all factors using MATLAB tool. Based on this we then generate three distributionmodels to study the combined likelihood of the variations. It also uses Monte Carlo simulation to understand total power usage. Through this work we can conclude that the power consumption of DFE ASICs is affected by a variety of factors. The power model and spread analysis can be usedto forecast and optimize power usage in 5G systems.

<div>Radio Frequency Power Amplifiers (PA) are essential components of wireless systems and nonlinear in a permanent way. So, high efficiency and linearity at a time are imperative for power amplifiers. However, it is hard to obtain because high efficiency Power Amplifiers are nonlinear and linear Power Amplifiers have poor efficiency. To meet both linearity and efficiency, the linearization techniques such as Digital Predistortion (DPD) has arrested the most attention in industrial and academic sectors due to provide a compromising data between efficiency and linearity. This thesis proposed on digital predistortion techniques to control nonlinear distortion in radio frequency transmitters. </div><div>By using predistortion technique, both linearity and efficiency can obtain. In this thesis a new generic Saleh model for use in memoryless nonlinear power amplifier (PA) behavioral modelling is used. The results are obtained by simulations through MATLAB and experiments. We explore the baseband 13.56 MHz Power Amplifier input and output relationships and reveal that they apparent differently when the Power Amplifier shows long-term, short-term or memory less effects. We derive a SIMULINK based static DPD design depend on a memory polynomial. A polynomial improves both the non-linearity and memory effects in the Power Amplifier. As PA characteristics differs from time to time and operating conditions, we developed a model to calculate the effectiveness of DPD. We extended our static DPD design model into an adaptive DPD test bench using Indirect Learning Architecture (ILA) to implement adaptive DPD which composed of DPD subsystem and DPD coefficient calculation. By this technique, the output of PA achieves linear, amplitude and phase distortions are eliminated, and spectral regrowth is prevented. </div><div>The advanced linearity performance executed through the strategies and methods evolved on this thesis can allow a higher usage of the capability overall performance of existing and emerging exceptionally performance PAs, and therefore an anticipated to have an effect in future wireless communication systems. </div>