Dans cette thèse est défendu l'intérêt d'évaluer la santé d'un système/objet industriel multi-composants à travers un bilan de santé multi-niveaux hiérarchiques. Elle a donc pour objet principal de justifier les éléments essentiels du concept de bilan de santé générique qui représente l'état réel d'un système sous la forme d'un vecteur d'indicateurs de différentes natures. Vis-à-vis de ce fondement, la thèse se focalise plus spécifiquement sur les fonctions de détection des anomalies-normalisation et agrégation d'indicateurs pour élaborer un index synthétique représentatif de l'état de santé global pour chaque élément du système. Il est ainsi proposé, une nouvelle approche de détection conditionnelle des anomalies. Cette approche a pour intérêt de quantifier la déviation pour chaque indicateur par rapport à son mode de comportement nominal tout en prenant en compte le contexte dans lequel évolue le système. Une extension à l'exploitation de l'intégrale de Choquet en tant qu'opérateur d'agrégation des indicateurs est aussi proposée. Cette extension concerne, d'une part, un processus d'apprentissage non supervisé des capacités pour le niveau le plus inférieur dans l'abstraction, à savoir celui des composants, et d'autre part, une approche de mise en oeuvre de leur inférence d'un niveau à l'autre. Ces propositions sont appliquées sur un moteur diesel de navire, système essentiel du projet BMCI du pôle MER-PACA dans lequel s'inscrit cette thèse / This work is addressing the health assessment of a multi-component system by means of multi-levels health check-up. Thus scientific Ph. D. objective aims to establish items of a generic health check-up concept. It focuses specifically on the functions of anomaly detection, normalization and aggregation of different indicators to develop a synthetic index representing the overall health status for each element within the system. In that way, it is proposed a new approach for detecting conditional anomalies. This approach has the advantage of quantifying the deviation for each indicator compared to its nominal behavior while taking into account the context in which the system operates. An extension of the Choquet integral used as an operator aggregating indicators is also proposed. This extension regards on the one hand, a process of an unsupervised learning of the capacity coefficients for the lowest level of abstraction, namely components level, and on the other hand, an approach to inference them from one level to another. These contributions are implemented on a ship diesel engine which is the most critical system for the BMCI project of the MER-PACA pole to which this thesis is attached

Submitted by Carmen Torres (carmensct@globo.com) on 2018-02-09T18:11:30Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MapeamentoBitsAdaptacao.pdf: 986310 bytes, checksum: 6e1b30f6ca34fc67df43f3141680c73a (MD5) / Approved for entry into archive by Edisangela Bastos (edisangela@ufpa.br) on 2018-02-16T16:12:49Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MapeamentoBitsAdaptacao.pdf: 986310 bytes, checksum: 6e1b30f6ca34fc67df43f3141680c73a (MD5) / Made available in DSpace on 2018-02-16T16:12:49Z (GMT). No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MapeamentoBitsAdaptacao.pdf: 986310 bytes, checksum: 6e1b30f6ca34fc67df43f3141680c73a (MD5) Previous issue date: 2017-09-29 / CNPq - Conselho Nacional de Desenvolvimento Científico e Tecnológico / Os codigos com matriz de vericação de paridade de baixa densidade (LDPC) tem sido adotados como estrategia de correção de erros em diversos padrões de sistemas de comunicação, como nos sistemas G.hn (padrão que unifica as redes domesticas) e IEEE 802.11n (padrão para redes sem o locais). Nestes sistemas com modulação de amplitude em quadratura (QAM) codicados com LDPC, mapear propriamente os bits codificados para os diferentes sub-canais, considerando o fato de os sub-canais terem diferentes qualidades, garante uma melhora no desempenho geral do sistema. Nesse sentido, esta Tese apresenta uma nova técnica de mapeamento de bits, baseada na suposição de que bits transmitidos em sub-canais \bons" ajudam bits transmitidos em sub-canais \ruins". Isto e possível através de algumas restrições impostas ao grafo de Tanner associado, semelhantes aos códigos Root-LDPC. A otimização deste mapeamento de bits utilizando curvas de transferência de informação extrínseca (EXIT charts) também e apresentada. Observa-se que esse mapeamento tem a vantagem de um espaço de busca de otimização reduzido quando aplicado ao sistema com modo de transmissão de portadora única. Além disso, em situações nas quais o espaço de busca não e tão reduzido, como em aplicações baseadas em multiplexação por divisão de frequência ortogonal (OFDM), chegou-se a uma simples regra pratica associada as restrições do mapeamento de bits que praticamente elimina a necessidade de uma otimização. Por fim, um estudo do impacto do nível de desequilíbrio de contabilidade através dos sub-canais sobre o desempenho do mapeamento de bits e apresentado. Os resultados das simulações mostram que a estratégia de mapeamento de bits melhora o desempenho do sistema, e que, na presença de variações do canal, o sistema pode, adaptativamente, aplicar um novo mapeamento de bits sem a necessidade de recorrer a uma otimização complexa, podendo ser muito útil em sistemas práticos. / Low-Density parity-check (LDPC) codes are being adopted as the error correction strategy in di erent system standards, such as the G.hn (home networking standard) and the IEEE 802.11n (wireless local standard). In these LDPC-coded quadrature amplitude modulation (QAM) systems, mapping the LDPC coded bits properly to the di erent sub-channels considering the fact that sub-channels have di erent qualities ensures an improved overall system performance. Accordingly, this thesis presents a new bit mapping technique based on the assumption that bits transmitted in \good" sub-channels, help bits transmitted in \bad" sub-channels. This can be made possible through some restrictions to be imposed on the associated Tanner graph, akin to Root-LDPC codes. An optimization of the root-like bit mapping through extrinsic information transfer (EXIT) charts analysis is also presented. We show that this mapping has the advantage of a reduced optimization search space when applied to single-carrier based systems. Moreover, in situations where the search space is not só reduced, such as in orthogonal frequency division multiplexing (OFDM)-based applications, we arrive at a rule of thumb associated with the bit mapping constraints that practically eliminates the need for an optimization. Finally, a study of the impact of the level of reliability imbalance across the sub-channels on the performance of the root-like bit mapping is presented. Simulation results show that the new bit mapping strategy improves performance, and that in the presence of channel variations, the system can, adaptively, apply a new bit mapping without the need of a complex optimization, which can be very useful in practical systems.

過去立法院常被譏為行政院的橡皮圖章，但隨著國內民主政治的快速發展，立法院已成為我國當前最重要的政治舞台，不管是各政黨或是政治人物，對於在立法院合議制度下，所形成的權力分享與利益分配，都有莫大的關注與興趣。再者，立法院職權之行使攸關人民生活財產的維護，在民主化的過程裡，代表民意的立法院，更背負著民眾的高度期待。因此，研究立法院之監督功能，對立法與行政之間的互動關係做一明確的界定與釐清，將有助於了解我國民主政治的建立與實踐民主化的進程。 本研究旨在探討立法院之監督功能，也因此擬先介紹民主國家國會監督概念，針對「監督」一詞，加以界定並分析其理論基礎。再針對各國憲政發展之比較，來了解何以要研究我國立法院監督功能，並從我國民主發展過程中，探討立法院扮演監督功能的意義與角色，最後試圖從法制規範層次與實務操作層次上，找尋出我國立法院所具有的監督效果，以達到探究其監督功能之目的。 從萬年國會到國會全面改選，乃至目前歷經六次修憲以來，我國國會體制逐漸落實立法院真正成為全國最高立法機關之制度設計，不過立法權如何有效落實其監督制衡行政權的功能，除了從靜態的憲法條文賦予的職權來分析，還必須透過動態的立法權行使過程加以探討。因此，本文先從民主憲政原理中的監督背景及其概念，假設我國在國會全面改選後，雖然行政部門過去的主導力量甚強，但立法權仍能發揮其監督行政權之功能，以立法院所行使的職權是否具有監督功能來分析，並觀察出立法院非制度面部分，具有的實際監督功能之機制，最後做出結論與提出建議。 本文分成六個部分。第一章緒論，介紹本論文研究背景、研究目的、概念界定、研究架構設定、文獻回顧、研究方法及研究範圍與限制；第二章國會監督功能之理論基礎，從形成國會的民主概念破題，來介紹國會監督功能之背景、意義、基礎、技術，以了解民主國家之國會監督功能；第三章我國立法院監督功能之介紹，從我國立法院形成之背景，來介紹立法院監督功能之背景、意義、基礎、技術，以呼應第二章；第四章法制規範層次之監督功能分析，是以監督對象為基礎來分析立法院的監督功能，文中將監督對象分成對人如同意權、彈劾權等；對機關如預算權的監督；對政策如法案權，再放置到四個重要民主政治概念（權力分立、代議政治、有限政府、權力制衡）中來檢驗，以了解其法源依據、規範作用及實質影響；第五章實務操作層次之監督功能分析，將提出具有實際運作而無法在法制層次探討如議事杯葛、政黨協商等非正式制度面之監督功能，從實務操作層次中，去探討其實質影響。第六章結論，提出研究過程中所得到之發現，及希冀提供後進研究者之建議。

In this work, a multilayer security solution for digital communication systems is provided by considering the joint effects of physical-layer security channel codes with application-layer cryptography. We address two problems: first, the cryptanalysis of error-prone ciphertext; second, the design of a practical physical-layer security coding scheme. To our knowledge, the cryptographic attack model of the noisy-ciphertext attack is a novel concept. The more traditional assumption that the attacker has the ciphertext is generally assumed when performing cryptanalysis. However, with the ever-increasing amount of viable research in physical-layer security, it now becomes essential to perform the analysis when ciphertext is unreliable. We do so for the simple substitution cipher using an information-theoretic framework, and for stream ciphers by characterizing the success or failure of fast-correlation attacks when the ciphertext contains errors. We then present a practical coding scheme that can be used in conjunction with cryptography to ensure positive error rates in an eavesdropper's observed ciphertext, while guaranteeing error-free communications for legitimate receivers. Our codes are called stopping set codes, and provide a blanket of security that covers nearly all possible system configurations and channel parameters. The codes require a public authenticated feedback channel. The solutions to these two problems indicate the inherent strengthening of security that can be obtained by confusing an attacker about the ciphertext, and then give a practical method for providing the confusion. The aggregate result is a multilayer security solution for transmitting secret data that showcases security enhancements over standalone cryptography.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and commercial implementations. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Using this paradigm, the run-time configurable and multi-rate VLSI architectures for the rate compatible array LDPC codes and irregular block LDPC codes are designed. Rate compatible array codes are considered for DSL applications. Irregular block LDPC codes are proposed for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. When compared with a recent implementation of an 802.11n LDPC decoder, the proposed decoder reduces the logic complexity by 6.45x and memory complexity by 2x for a given data throughput. When compared to the latest reported multi-rate decoders, this decoder design has an area efficiency of around 5.5x and energy efficiency of 2.6x for a given data throughput. The numbers are normalized for a 180nm CMOS process. Properly designed array codes have low error floors and meet the requirements of magnetic channel and other applications which need several Gbps of data throughput. A high throughput and fixed code architecture for array LDPC codes has been designed. No modification to the code is performed as this can result in high error floors. This parallel decoder architecture has no routing congestion and is scalable for longer block lengths. When compared to the latest fixed code parallel decoders in the literature, this design has an area efficiency of around 36x and an energy efficiency of 3x for a given data throughput. Again, the numbers are normalized for a 180nm CMOS process. In summary, the design and analysis details of the proposed architectures are described in this dissertation. The results from the extensive simulation and VHDL verification on FPGA and ASIC design platforms are also presented.

Low Density Parity Check (LDPC) codes are the parity check codes of long block length, whose parity check matrices have relatively few non-zero entries. To improve the performance at relatively short block lengths, LDPC codes are constructed by either pseudo-random or quasi-cyclic methods instead of random construction methods. In this thesis, pseudo-random code construction methods, the effects of closed loops and the graph connectivity on the performance of pseudo-random LDPC codes are investigated. Moreover, quasi-cyclic LDPC codes, which have encoding and storage advantages over pseudo-random LDPC codes, their construction methods and performances are reviewed. Finally, performance comparison between pseudo-random and quasi-cyclic LDPC codes is given for both regular and irregular cases.

Traditional solutions to information security in communication systems act in the application layer and are oblivious to the effects in the physical layer. Physical-layer security methods, of which information-theoretic security is a special case, try to extract security from the random effects in the physical layer. In information-theoretic security, there are two asymptotic notions of secrecy---weak and strong secrecy This dissertation investigates the problem of information-theoretic strong secrecy on the binary erasure wiretap channel (BEWC) with a specific focus on designing practical codes. The codes designed in this work are based on analysis and techniques from error-correcting codes. In particular, the dual codes of certain low-density parity-check (LDPC) codes are shown to achieve strong secrecy in a coset coding scheme. First, we analyze the asymptotic block-error rate of short-cycle-free LDPC codes when they are transmitted over a binary erasure channel (BEC) and decoded using the belief propagation (BP) decoder. Under certain conditions, we show that the asymptotic block-error rate falls according to an inverse square law in block length, which is shown to be a sufficient condition for the dual codes to achieve strong secrecy. Next, we construct large-girth LDPC codes using algorithms from graph theory and show that the asymptotic bit-error rate of these codes follow a sub-exponential decay as the block length increases, which is a sufficient condition for strong secrecy. The secrecy rates achieved by the duals of large-girth LDPC codes are shown to be an improvement over that of the duals of short-cycle-free LDPC codes.

Die vorliegende Ausgabe untersucht für den Eigenbetrieb Abwasserbeseitigung Bautzen die Auswirkungen des demografischen Wandels auf die Gebühren für das Jahr 2025. Aufgrund der Tatsache, dass der Schmutzwasseranfall in der Siedlungsentwässerung von vielen Faktoren abhängig ist, wird eine Methode gesucht, diese zu identifizieren und zu prognostizieren. Eine geeignete Methode stellt die Szenarioanalyse dar, welche in dieser Arbeit eingehend erörtert wird. Darüber hinaus wird ein geeignetes Vorgehen für eine Analyse in der Siedlungsentwässerung vorgeschlagen. Dieses Vorgehen wird in der Praxis auf den Eigenbetrieb Abwasserbeseitigung Bautzen angewandt. Somit dient diese Arbeit als Leitfaden und Beispielanwendung für eine Szenarioanalyse und kann auf alle Unternehmen der Abwasserentsorgung übertragen werden. Neben dem demografischen Wandel, der sich in erster Linie durch einen Bevölkerungsrückgang und eine Alterung der Bevölkerung äußert, können die Faktoren: Lebensstil/Verbrauchsgewohnheit, Art und Anzahl der Industrie- und Gewerbebetriebe, Umweltbewusstsein, Wohlstand/Bildung, Rechtsnormen, Erwerbstätigkeit und spezifischer Wasserverbrauch, mit Hilfe mathematischer Methoden identifiziert werden. Diese Größen stellen Deskriptoren dar und beeinflussen die Schmutzwassermenge langfristig am stärksten. Die Faktoren werden in dieser Arbeit speziell für Bautzen prognostiziert und ein Entwicklungsrahmen vorgegeben. Die vielen Ausprägungsmöglichkeiten dieser Größen lassen die Bildung einer Vielzahl von Szenarien zu, welche auf Konsistenz geprüft und von diesen konsistenten Szenarien wiederum vier ausgewählt werden. Die Umlegung der Szenarien auf die Gebühren erfordert eine gesonderte Betrachtung der gesetzlichen Regelungen und Auflagen, die es zu beachten gilt und ebenfalls, detailliert mit dieser Arbeit erfolgt. Darüber hinaus werden wichtige Hinweise für eine Gebührenprognose gegeben.

本研究旨在探討直轄市山地原住民區改制前後，原為官派制轉換成民選制的區，比較兩種制度在地方上的治理運作與模式，以表現不同制度在相同環境、事務時所產生的運作差異，一方面評估不同制度下之運作；方面評估制度中的民意制衡能力。最後分析民選制與官派制於治理上的優缺點和差異，並對當前制度提出相應的改善建議。 本研究採用的研究方法如下： 1.個案研究法：選定新北市烏來區為個案，觀察制度轉換之差異所造成的影響。 2.文獻分析法：整理分析相關文書資料以比較官派制與民選制的結構、機制之差異。 3.深入訪談法：選定直轄市山地原住民區改制前後，擔任行政與民代職務者，進行職 責與實務的訪談，調查制度差異對行為與結果的影響，以及地方感受跟評價。 / The case study is research to the mountain indigenous districts of special municipalities, the former official system is converted into an elected system of district.By comparing the models and practices of these two local governance systems brought by the institutional reform, which has led our attention to the differences of behavior and reaction the two systems have while put in the same environment and under the same government affairs, this present study evaluates the two systems with special focus on their administrative performance and check-and-balance capability of the public sector. The ultimate purpose of this study is to analyze the merits and limits of elected representation and official appointment and through observing one real case, and finally propose advices to improve the current system. Methodologies adopted in this study include: 1.Case study: Wilai District of New Taipei City is chosen to observe the impact of institutional reform. 2.Literature analysis: Relevant documents and data are collected and analyzed for the comparison of official appointment and elected representation in their organizational and functional differences. 3.In-depth interview: Administrative officials and elected representatives who have experienced the transition are interviewed about their duty change and practical exercise of governance, in hope to investigate behavioral and consequential influences the new system has caused, and collect feedback and evaluation from local government.

This item contains the agenda, minutes, and attachments for the Faculty Senate meeting on this date. There may be additional materials from the meeting available at the Faculty Center.