Aufgrund von guten Eigenschaften als Kupferdiffusionsbarriere und guter elektrischer Leitfähigkeit könnte sich Ruthenium und Ruthenium basierte Legierungen als Kupferdiffusionsbarriere eignen. Auf eine theoretische Aufarbeitung von Elektromigrationsmechanismen und in der Praxis eingesetzte Elektromigrationsteststrukturen folgen beschleunigte elektrische Elektromigrationstestergebnisse. Es konnte gezeigt werden, dass das System Kupfer, Ruthenium, Tantalnitrid Elektromigrationsstabiler als das konventionelle System Kupfer, Tantal, Tantalnitrid ist.

The effects of intermetallic compound (IMC) formation on reliability of Pb-free Sn-based solders for flip chip and three-dimensional (3D) interconnects were studied. The dissertation is organized into four parts. In the first part, the effect of Sn grain orientation on electromigration (EM) reliability of Pb-free Sn-based flip chip solder joints was studied. The Sn grain microstructure in flip chip solder joints was characterized using the electron backscatter diffraction (EBSD) technique, and wa found to be closely related to the EM failure mechanims. The approach to grain structure optimization for improved EM reliability was also explored. In addition to the experimental work, a kinetic analysis was formulated to investigate the early EM degradation mechanism in Sn-based solder joints with Ni under-bump metallization (UMB). The aforementioned kinetic analysis, the intrinsic diffusion coefficients were not readily available in the literature. In the second part of the work, a Monte Carlo method known as simulated annealing was applied to estimate the unknown diffusion coefficients using a multi-parameter optimization method by fitting to experimental measurements. The intrinsic diffusion coefficients of Ni and Sn in Ni₃Sn₄ between 150 and 200°C, and those of Cu and Sn in Cu₃Sn and Cu₆Sn₅ between 120 and 200°C were estimatd. The activation energies for these diffusion coefficients were also determined. Together, this provides the diffusivity parameters to predict the intermetallic growth as a function of temperature. The third objective focused on the EM reliability of Sn-based microbump joints in 3D interconnects with through-silicon vias (TSVs). No EM-induced bump failure was observed, showing a robust EM reliability in microbumps. High temperature thermal annealing test was also performed on microbumps with three different metallizations in an effort to explore structural and process optimization. Finally, interfacial reaction induced stress in IMC microbumps was investigated. A numerial analysis was formulated to study the concurrent diffusion, phase transformation, and deformation in the process of IMC formation. Stress generation due to unbalanced diffusion rates and volumetric change upon phase transformation was considered. The coupled analysis was applied to investigate Ni₃Sn₄ growth in the Ni-Sn microbumping system. A simulation approach based on finite difference method with moving boundaries was employed to numerically solve stress evolution in Ni₃Sn₄. The equilibrium stress was also investigated using a modified model with a finite thickness of solder. Simulation predictions were found to be in good qualitative agreement with experimental observations. / text

L'electromigration est identifiée comme la principale cause de dégradation des interconnexions en cuivre limitant ainsi la fiabilité des produits issus de la microélectronique. Dans ces travaux nous proposons d'approfondir notre connaissance de ce phénomène en étudiant le lien qu'il présente avec les paramètres morphologiques du cuivre. Dans ce but, la technique de diffraction des électrons rétrodiffusés est utilisée. Nous avons d'abord développé les méthodes de préparation et d'acquisition nécessaires afin de pouvoir caractériser les structures issues des technologies 45 nm et au-delà que nous avons choisies pour cette étude. Un lien entre les joints de grains de forte désorientation et la localisation des cavités a alors pu être mis en évidence. Nous avons ensuite tenté de modifier la microstructure du cuivre pour impacter la fiabilité sans succès. Finalement, c'est l'intégration de nouveaux matériaux (Al, Co) renforçant l'interface supérieure, chemin de diffusion du phénomène, qui semble être la voie à adopter pour améliorer la résistance des lignes à l'électromigration.

The processes of grain boundary grooving and cathode voiding which are important in determining the life times of thin films connecting the transistors in an integrated circuit are investigated by introducing a new mathematical model, which flows from the fundamental postulates of irreversible thermodynamics, accounting for the effects of applied electric field and thermal stresses. The extensive computer studies on the triple junction displacement dynamics shows that it obeys the first order reaction kinetics at the transient stage, which is followed by the familiar time law as , in the normalized time and space domain, at the steady state regime in the absence of the electric field (EF). The application of EF doesn&rsquo / t modify this time law very / but puts only an abrupt upper limit for the groove depth and fixes the total elapse time for that event, which is found to be inversely proportional with the electron wind intensity parameter. The drift in the cathode edge due to the surface diffusion along the side walls is simulated under the constant current regime. An analytical formula is obtained in terms of system parameters, which shows well defined threshold level for the onset of electromigration induced cathode drift, showing an excellent agreement with the reported experimental values in the literature.

The Electromigration-induced failure of metallic interconnects is a complicated process, which involves flux divergence, vacancy and atom accumulation with or without compositional variations, void and hillocks nucleation, growth and shape changes. Hillocks and surface void dynamics in connection with the critical morphological evaluation have been investigated in order to understand the conditions under which premature failure of metallic thin interconnects occur. In this thesis, an interconnect is idealized as a two dimensional electrically conducting strip which contains gaussian form hillock or edge void. Indirect boundary element is used to predict the evolution of the surface after the applied electric field. Computer simulation results show that the surface crystal structure of is extremely important in the determination of the life time of thin film single crystal interconnect lines. Under the applied electrostatic field not only the degree of rotational symmetry (parameter, m) but also the orientation of the surface plane play dominant role in the development of the surface topology and the formation of the fatal EM induced voids. The degree of anisotropy in the surface diffusion coefficient, and the intensity of the electron wind parameter may have great influence on the evolution regime actually taking place on the surfaces and at sidewalls of the interconnects.

A Eletromigração (EM) nas interconexões de metal em um chip é um mecanismo crítico de falhas de confiabilidade em tecnologias de escala nanométrica. Os trabalhos na literatura que abordam os efeitos da EM geralmente estão preocupados com estes efeitos nas redes de distribuição de potência e nas interconexões entre as células. Este trabalho aborda o problema da EM em outro aspecto, no interior das células, e aborda especificamente o problema da eletromigração em interconexões de saída, Vdd e Vss dentro de uma célula padrão onde há poucos estudos na literatura que endereçam esse problema. Até onde sabe-se, há apenas dois trabalhos na literatura que falam sobre a EM no interior das células. (DOMAE; UEDA, 2001) encontrou buracos formados pela EM nas interconexões de um inversor CMOS e então propôs algumas ideias para reduzir a corrente nos segmentos de fio onde formaram-se buracos. O outro trabalho, (JAIN; JAIN, 2012), apenas cita que a EM no interior das células padrão deve ser verificada e a frequência segura das células em diferentes pontos de operação deve ser modelada. Nenhum trabalho da literatura analisou e/ou modelou os efeitos da EM nos sinais dentro das células. Desta forma, este é o primeiro trabalho a usar o posicionamento dos pinos para reduzir os efeitos da EM dentro das células. Nós modelamos a eletromigração no interior das células incorporando os efeitos de Joule heating e a divergência da corrente e este modelo é usado para analisar o tempo de vida de grandes circuitos integrados. Um algoritmo eficiente baseado em grafos é desenvolvido para acelerar a caracterização da EM no interior das células através do cálculos dos valores de corrente média e RMS. Os valores de corrente computados por esse algoritmo produzem um erro médio de 0.53% quando comparado com os valores dados por simulações SPICE. Um método para otimizar a posição dos pinos de saída, Vdd e Vss das células e consequentemente otimizar o tempo de vida do circuito usando pequenas modificações no leiaute é proposto. Para otimizar o TTF dos circuitos somente o arquivo LEF é alterado para evitar as posições de pino críticas, o leiaute da célula não é alterado. O tempo de vida do circuito pode ser melhorado em até 62.50% apenas evitando as posições de pino críticas da saída da célula, 78.54% e 89.89% evitando as posições críticas do pino de Vdd e Vss, respectivamente Quando as posições dos pinos de saída, Vdd e Vss são otimizadas juntas, o tempo de vida dos circuitos pode ser melhorado em até 80.95%. Além disso, nós também mostramos o maior e o menor tempo de vida sobre todos as posições candidatas de pinos para um conjunto de células, onde pode ser visto que o tempo de vida de uma célula pode ser melhorado em até 76 pelo posicionamento do pino de saída. Além disso, alguns exemplos são apresentados para explicar porque algumas células possuem uma melhora maior no TTF quando a posição do pino de saída é alterada. Mudanças para otimizar o leiaute das células são sugeridas para melhorar o tempo de vida das células que possuem uma melhora muito pequena no TTF através do posicionamento dos pinos. A nível de circuito, uma análise dos efeitos da EM é apresentada para as diferentes camadas de metal e para diferentes comprimentos de fios para os sinais (nets) que conectam as células. / Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. Usually works in the literature that address EM are concerned with power network EM and cell to cell interconnection EM. This work deals with another aspect of the EM problem, the cell-internal EM. This work specifically addresses the problem of electromigration on signal interconnects and on Vdd and Vss rails within a standard cell. Where there are few studies in the literature addressing this problem. To our best knowledge we just found two works in the literature that talk about the EM within a cell. (DOMAE; UEDA, 2001) found void formed due to electromigration in the interconnection portion in a CMOS inverter and then proposes some ideas to reduce the current through the wire segments where the voids were formed. The second work, (JAIN; JAIN, 2012), just cites that the standard-cell-internal-EM should be checked and the safe frequency of the cells at different operating points must be modeled. No previous work analyzed and/or modeled the EM effects on the signals inside the cells. In this way, our work is the first one to use the pin placement to reduce the EM effects inside of the cells. In this work, cell-internal EM is modeled incorporating Joule heating effects and current divergence and is used to analyze the lifetime of large benchmark circuits. An efficient graph-based algorithm is developed to speed up the characterization of cell-internal EM. This algorithm estimates the currents when the pin position is moved avoiding a new characterization for each pin position, producing an average error of just 0.53% compared to SPICE simulation. A method for optimizing the output, Vdd and Vss pin placement of the cells and consequently to optimize the circuit lifetime using minor layout modifications is proposed. To optimize the TTF of the circuits just the LEF file is changed avoiding the critical pin positions, the cell layout is not changed. The circuit lifetime could be improved up to 62.50% at the same area, delay, and power because changing the pin positions affects very marginally the routing. This lifetime improvement is achieved just avoiding the critical output pin positions of the cells, 78.54% avoiding the critical Vdd pin positions, 89.89% avoiding the critical Vss pin positions and up to 80.95% (from 1 year to 5.25 years) when output, Vdd, and Vss pin positions are all optimized simultaneously. We also show the largest and smallest lifetimes over all pin candidates for a set of cells, where the lifetime of a cell can be improved up to 76 by the output pin placement. Moreover, some examples are presented to explain why some cells have a larger TTF improvement when the output pin position is changed. Cell layout optimization changes are suggested to improve the lifetime of the cells that have a very small TTF improvement by pin placement. At circuit level, we present an analysis of the EM effects on different metal layers and different wire lengths for signal wires (nets) that connect cells.

abstract: Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer is employed. The electrical and structural characterization of hole transfer layers (HTLs) in OSCs reveals MoO3 is the compatible HTL for TAgT anode. In the end, the reactive ink printed Ag film for solar cell contact application is studied by characterizing its electromigration lifetime. A percolative model is proposed and validated for predicting the resistivity and lifetime of printed Ag thin films containing porous structure. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2017

A Eletromigração (EM) nas interconexões de metal em um chip é um mecanismo crítico de falhas de confiabilidade em tecnologias de escala nanométrica. Os trabalhos na literatura que abordam os efeitos da EM geralmente estão preocupados com estes efeitos nas redes de distribuição de potência e nas interconexões entre as células. Este trabalho aborda o problema da EM em outro aspecto, no interior das células, e aborda especificamente o problema da eletromigração em interconexões de saída, Vdd e Vss dentro de uma célula padrão onde há poucos estudos na literatura que endereçam esse problema. Até onde sabe-se, há apenas dois trabalhos na literatura que falam sobre a EM no interior das células. (DOMAE; UEDA, 2001) encontrou buracos formados pela EM nas interconexões de um inversor CMOS e então propôs algumas ideias para reduzir a corrente nos segmentos de fio onde formaram-se buracos. O outro trabalho, (JAIN; JAIN, 2012), apenas cita que a EM no interior das células padrão deve ser verificada e a frequência segura das células em diferentes pontos de operação deve ser modelada. Nenhum trabalho da literatura analisou e/ou modelou os efeitos da EM nos sinais dentro das células. Desta forma, este é o primeiro trabalho a usar o posicionamento dos pinos para reduzir os efeitos da EM dentro das células. Nós modelamos a eletromigração no interior das células incorporando os efeitos de Joule heating e a divergência da corrente e este modelo é usado para analisar o tempo de vida de grandes circuitos integrados. Um algoritmo eficiente baseado em grafos é desenvolvido para acelerar a caracterização da EM no interior das células através do cálculos dos valores de corrente média e RMS. Os valores de corrente computados por esse algoritmo produzem um erro médio de 0.53% quando comparado com os valores dados por simulações SPICE. Um método para otimizar a posição dos pinos de saída, Vdd e Vss das células e consequentemente otimizar o tempo de vida do circuito usando pequenas modificações no leiaute é proposto. Para otimizar o TTF dos circuitos somente o arquivo LEF é alterado para evitar as posições de pino críticas, o leiaute da célula não é alterado. O tempo de vida do circuito pode ser melhorado em até 62.50% apenas evitando as posições de pino críticas da saída da célula, 78.54% e 89.89% evitando as posições críticas do pino de Vdd e Vss, respectivamente Quando as posições dos pinos de saída, Vdd e Vss são otimizadas juntas, o tempo de vida dos circuitos pode ser melhorado em até 80.95%. Além disso, nós também mostramos o maior e o menor tempo de vida sobre todos as posições candidatas de pinos para um conjunto de células, onde pode ser visto que o tempo de vida de uma célula pode ser melhorado em até 76 pelo posicionamento do pino de saída. Além disso, alguns exemplos são apresentados para explicar porque algumas células possuem uma melhora maior no TTF quando a posição do pino de saída é alterada. Mudanças para otimizar o leiaute das células são sugeridas para melhorar o tempo de vida das células que possuem uma melhora muito pequena no TTF através do posicionamento dos pinos. A nível de circuito, uma análise dos efeitos da EM é apresentada para as diferentes camadas de metal e para diferentes comprimentos de fios para os sinais (nets) que conectam as células. / Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. Usually works in the literature that address EM are concerned with power network EM and cell to cell interconnection EM. This work deals with another aspect of the EM problem, the cell-internal EM. This work specifically addresses the problem of electromigration on signal interconnects and on Vdd and Vss rails within a standard cell. Where there are few studies in the literature addressing this problem. To our best knowledge we just found two works in the literature that talk about the EM within a cell. (DOMAE; UEDA, 2001) found void formed due to electromigration in the interconnection portion in a CMOS inverter and then proposes some ideas to reduce the current through the wire segments where the voids were formed. The second work, (JAIN; JAIN, 2012), just cites that the standard-cell-internal-EM should be checked and the safe frequency of the cells at different operating points must be modeled. No previous work analyzed and/or modeled the EM effects on the signals inside the cells. In this way, our work is the first one to use the pin placement to reduce the EM effects inside of the cells. In this work, cell-internal EM is modeled incorporating Joule heating effects and current divergence and is used to analyze the lifetime of large benchmark circuits. An efficient graph-based algorithm is developed to speed up the characterization of cell-internal EM. This algorithm estimates the currents when the pin position is moved avoiding a new characterization for each pin position, producing an average error of just 0.53% compared to SPICE simulation. A method for optimizing the output, Vdd and Vss pin placement of the cells and consequently to optimize the circuit lifetime using minor layout modifications is proposed. To optimize the TTF of the circuits just the LEF file is changed avoiding the critical pin positions, the cell layout is not changed. The circuit lifetime could be improved up to 62.50% at the same area, delay, and power because changing the pin positions affects very marginally the routing. This lifetime improvement is achieved just avoiding the critical output pin positions of the cells, 78.54% avoiding the critical Vdd pin positions, 89.89% avoiding the critical Vss pin positions and up to 80.95% (from 1 year to 5.25 years) when output, Vdd, and Vss pin positions are all optimized simultaneously. We also show the largest and smallest lifetimes over all pin candidates for a set of cells, where the lifetime of a cell can be improved up to 76 by the output pin placement. Moreover, some examples are presented to explain why some cells have a larger TTF improvement when the output pin position is changed. Cell layout optimization changes are suggested to improve the lifetime of the cells that have a very small TTF improvement by pin placement. At circuit level, we present an analysis of the EM effects on different metal layers and different wire lengths for signal wires (nets) that connect cells.

abstract: With increasing concerns of the intrinsic toxicity of lead (Pb) in electronics, a series of tin (Sn) based alloys involving silver (Ag) and copper (Cu) have been proposed as replacements for Pb-Sn solder and widely accepted by industry. However, they have a higher melting point and often exhibit poorer damage tolerance than Pb-Sn alloys. Recently, a new class of alloys with trace amount of rare-earth (RE) elements has been discovered and investigated. In previous work from Prof. Chawla's group, it has been shown that cerium (Ce)-based Pb-free solder are less prone to oxidation and Sn whiskering, and exhibit desirable attributes of microstructural refinement and enhanced ductility relative to lanthanum (La)-based Sn-3.9Ag-0.7Cu (SAC) alloy. Although the formation of RESn3 was believed to be directly responsible for the enhanced ductility in RE-containing SAC solder by allowing microscopic voids to nucleate throughout the solder volume, this cavitation-based mechanism needs to be validated experimentally and numerically. Additionally, since the previous study has exhibited the realistic feasibility of Ce-based SAC lead-free solder alloy as a replacement to conventional SAC alloys, in this study, the proposed objective focuses on the in in-depth understanding of mechanism of enhanced ductility in Ce-based SAC alloy and possible issues associated with integration of this new class of solder into electronic industry, including: (a) study of long-term thermal and mechanical stability on industrial metallization, (b) examine the role of solder volume and wetting behavior of the new solder, relative to Sn-3.9Ag-0.7Cu alloys, (c) conduct experiments of new solder alloys in the form of mechanical shock and electromigration. The research of this new class alloys will be conducted in industrially relevant conditions, and the results would serve as the first step toward integration of these new, next generation solders into the industry. / Dissertation/Thesis / Ph.D. Materials Science and Engineering 2012

abstract: Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current density is of great concern affecting the reliability of the entire microelectronics systems. This paper reviews electromigration in Pb- free solders, focusing specifically on Sn0.7wt.% Cu solder joints. Effect of texture, grain orientation, and grain-boundary misorientation angle on electromigration and intermetallic compound (IMC) formation is studied through EBSD analysis performed on actual C4 bumps. / Dissertation/Thesis / M.S. English 2013