Minskad effektförbrukning har blivit mer och mer intressant i takt med att fler produkter blir mobila. I artikeln Parallel Implementation of Linear Feedback Shift Registers for Low Power Applications, beskriver Menahem Lowy en metod för att konstruera slumptalsgeneratorer. Dessa är tänkta att vara effektsnålare än en vanlig enkel slumptalsgenerator, med återkopplat skiftregister. I det här examensarbetet har sex slumptalsgeneratorer konstruerats i VHDL. Två är baserade på Lowy’s metod och två är parallella varianter av dessa. Dessutom har en seriell slumptalsgenerator med återkopplat skiftregister och en parallell variant konstruerats som jämförelse. Dessa slumptalsgeneratorer har simulerats med avseende på effektförbrukningen. Detvisar sig att den bästa slumptalsgeneratorn, räknat i effekt per bit, är den parallella varianten av slumptalsgeneratorn med återkopplat skiftregister. / Reduced power consumption have become more and more of interest as more products are becoming mobile. In the article Implementation of Linear Feedback Shift Registers for Low Power Applications, Menahem Lowy describes a method of designing randombit-generators. In this project, six random bit-generators have been designed in VHDL. Two of these are based on Lowy’s method, and two are parallel variants of these. In addition, a serial feedback shift register and a parallel variant of it, have been designed for comparison. These randombit- generators have then been simulated with respect to the power consumption. It turnes out that the best randombit-generator, considering the effect per bit, is the parallel variant of the feedback shift register.

Detta examensarbete syftar till att skapa en modulgenerator som automatiskt genererar matchade motstånd. Med hjälp av sådana motstånd kan prestandan i integrerade kretsar förbättras. Modulgeneratorn som konstruerats klarar av att generera två eller flera matchade motstånd. Programmet skapar med hjälp av indata från konstruktören en färdig layout som kan användas somett byggblock i integrerade kretsar. Examensarbetet har slutförts och programmet har använts för att generera matchade motstånd till två större layouter vid institutionen för Elektroniksystem. / The aim of this thesis is to create a program that automatically generates matched resistors. By using such resistors the performance of integrated circuits can be improved. The program can generate two or more matched resistors. With a set of input parameters the user is able to generate a customized matched resistor. The project has been completed and the program has been used to generate matched resistors for two bigger layouts at the department of Electrical Engineering.

Telia Telesvar is an automatic anwering machine that is provided in your stationary telephone at home. The drawback of this is that you cannot see if anyone has called you. This report describes how a terminal for Telias Telesvar could be designed. Telesvar terminal will show in a display if anyone called you and show the incoming number. It will also play the spoken message in a built in speaker. The design is based on some key components, LCD (Liquid Crystal Display) and DTMF (Dual Tone Multiple Frequency) and PIC16F877 microcontroller. These components are also described in the report.

Denna rapport behandlar akustisk undervattenskommunikation. I rapporten tas olika aspekter upp på modulering, demodulering, kanalutjämning, den akustiska undervattenskanalens egenskaper samt andra fenomen och problem som kan uppkomma vid undervattenskommunikation. Speciellt har vikten i rapporten lagts vid adaptiva kanalutjämnare. Utifrån olika simuleringar provades en undervattenskommunikationsmodell under fältmässiga förhållanden. Resultatet av utprovningen visade att differentiellt fasskift i kombination med en kanalutjämnare fungerade väl under rådande förhållanden. I rapportens senare del beskrivs ett undervattenskommunikationssystem uppbyggd kring en Xilinx Spartan2 FPGA. Konstruktionen är resultatet av de teoretiska och praktiska slutsatser som framkommit under arbetets gång.

The purpose of this thesis was to implement a serial communication port model for a digital signal processor. It is a behavioral model, developed using VHDL, that is instruction comparisable to the Motorola digital signal processor DSP 56002. It supports five different data transfer modes and provides a programmable baud rate generator. This report starts out by giving a description of the external port, port C, the pin control logic and general purpose functionality. Then a more detailed description of the three pin dedicated serial communication interface is presented, the different operating modes and the baud rate generator are described.

The goal of this work is to summarize the calculations for scaling and noise of twoportadaptor. Two different methods has been described and used for the final results.

The purpose with this examination is to build a measureequipment to AerotechTelub AB (AT), who will registrate fault in SRAM-memory in contact with cosmic radiation. The equipment will be created around developcard from Memec Design with FPGA from Xilinx. The logic in the FPGA will be implemented with the hardwaredescribed language VHDL. The SRAM-memory that will be tested is build in CMOS-teknologi. The memorycells will be loaded with a predecided bitpattern. Changes in the memorycells will be registrated together with the adress where the fault came up. The equipment will be used of AT at the measuring they use to do in special laboratories that can give cosmic radiation.

The last few decades the development in the field of electronics has been huge. The components performance gets better at the same time as the manufacturing cost decreases. Many of the design moments that have to be done, are done automatically today, but it can get better. Especially for analog circuit design. At Electronic System in Linköpings universitet, research is in progress to develop a tool that can design analog circuits in reasonable time. It means that it has to size the components (transistors, resistances, capacitances etc), so that the circuit can fulfill the performance requirements. An optimization method in conjunction with derived equations for the circuit performance is used to solve this task. The tool is created to design e.g. analog amplifiers. The goal is to decrease the design time and at the same time achieve better circuit performance. This tool has been tested on three different circuits, a power-amplifier, a Nested Miller Compensated amplifier with an active feedback (Active Nested Miller Compensation) and a Nested Miller Compensated amplifier without an active feedback (Nested Miller Compensation). In this report the results from the designing tests are presented.

An important part in the design of analog integrated circuits is to create reference voltages and currents with well defined values. To accomplish this on-chip, so called bandgap reference circuits are commonly used. A typical application for reference voltages is in analog-to-digital conversion, where the input voltage is compared to several reference levels in order to determine the corresponding digital value. The emphasis in this thesis work lies on theoretical understanding of the performance limitations as well as the design of a bandgap reference circuit, BGR. In this project, a comprehensive study of bandgap circuits is done in the first stage. Then investigations on parameter variations like Vdd, number of bipolars, W/L of PMOS, DC gain of Opamp, RL and CL are done for a PTAT current generator circuit. This PTAT current generator circuit is a part of the implemented BGR circuit based on [10], which is capable of producing an output reference voltage of 0.75 V when the supply voltage is 1 V. All of these circuits are implemented in a 0.35u CMOS technology.

<p>This report deals with the design of a controller for SmartMedia™ flash memory cards, based on a hardware description found in the SmartMedia™ Interface Library - SMIL. </p><p>The design was made on logic gate level, using standard cells in OrCAD Capture. After simulation of the design in PSpice A/D, it was exported as an EDIF netlist, which was used to make a chip layout in L-Edit, a layout tool for making integrated circuits. The layout was made using a method called Standard Place and Route - SPR, where the layout tool places standard cells from a library and connects them according to the EDIF netlist. </p><p>A netlist which could be simulated in PSpice was extracted from the finished chip layout to verify that the function of the design was the same as before the transition from schematic to layout. </p><p>The standard cells in the library used to make the chip layout have to meet certain criteria in order for both SPR and extraction to work and this is also discussed.</p>