Fabrication of high-performance electronic devices using the novel semiconductors is essential for developing future electronics which can be applicable in large-area, flexible and transparent displays, sensors and solar cells. One of the major bottlenecks in the fabrication of high-performance devices is a large interfacial barrier formation at metal/semiconductor interface originated from Schottky barrier and interfacial dipole barrier which causes inefficient charge injection at the interface. Therefore, having a favorable contact at electrode/semiconductor is highly desirable for high-performance devices fabrication. In this dissertation, the fabrication of nanoelectronic devices and investigation of their transport properties using carbon nanotubes (CNTs) and graphene as electrode materials will be shown. I investigated two types of devices using (i) semiconducting CNTs, and (ii) organic semiconductors (OSC). In the first part of this thesis, I will demonstrate the fabrication of high-performance solution-processed highly enriched (99%) semiconducting CNT thin film transistors (s-CNT TFTs) using densely aligned arrays of metallic CNTs (m-CNTs) for source/drain electrodes. From the electronic transport measurements at room temperature, significant improvements of field-effect mobility, on-conductance, transconductance and current on/off ratio for m-CNT/s-CNT devices were found compared to control palladium (Pd contacted s-CNT devices. From the temperature dependent transport investigation, a lower Schottky barrier height for the m-CNT/s-CNT devices was found compared to the devices with control metal electrodes. The enhanced device performance can be attributed to the unique device geometry as well as strong ?- ? interaction at m-CNT/s-CNT interfaces. In addition, I also investigated s-CNT TFTs using reduced graphene oxide (RGO) electrodes. In the second part of my thesis, I will demonstrate high-performance organic field-effect transistors (OFETs) using different types of graphene electrodes. I show that the performance of OFETs with pentacene as OSC and RGO as electrode can be continuously improved by increasing the carbon sp2 fraction of RGO. The carbon sp2 fractions of RGO were varied by controlling the reduction time. When compared to control Pd electrodes, the mobility of the OFETs shows an improvement of ?200% for 61% sp2 fraction RGO, which further improves to ?500% for 80% RGO electrode. Similarly, I show that when the chemical vapor deposition (CVD) graphene film is used as electrodes in fabricating OFET, the better performance is observed in comparison to RGO electrodes. Our study suggests that, in addition to ?-? interaction at graphene/pentacene interface, the tunable electronic properties of graphene as electrode have a significant role in OFETs performance. For a fundamental understanding of the interface, we fabricated short-channel OFETs with sub-100nm channel length using graphene electrode. From the low temperature electronic transport measurements, a lower charge injection barrier was found compared to control metal electrode. The detailed investigations reported in this thesis clearly indicated that the use of CNT and graphene as electrodes can improve the performance of future nanoelectronic devices.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24623号 / 工博第5129号 / 新制||工||1980(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 川上 養一, 准教授 浅野 卓 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

The aggressive reduction of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has resulted in an exponential increase in computing power. Stemming from increases in device density and substantial progress in materials science and transistor design, the integrated circuit has seen continual performance improvements and simultaneous reductions in operating power (VDD). Nevertheless, existing Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are rapidly approaching the physical limits of their scaling potential. New material innovations, such as binary group IV or ternary III-V compound semiconductors, and novel device architectures, such as the tunnel field-effect transistor (TFET), are projected to continue transistor miniaturization beyond the Si CMOS era. Unlike conventional MOSFET technology, TFETs operate on the band-to-band tunneling injection of carriers from source to channel, thereby resulting in steep switching characteristics. Furthermore, narrow bandgap semiconductors, such as germanium (Ge) and InxGa1-xAs, enhance the ON-state current and improve the switching behavior of TFET devices, thus making these materials attractive candidates for further study. Moreover, epitaxial growth of Ge on InxGa1-xAs results in tensile stress (ε) within the Ge thin-film, thereby giving device engineers the ability to tune its material properties (e.g., mobility, bandgap) via strain engineering and in so doing enhance device performance. For these reasons, this research systematically investigates the material, optical, electronic transport, and heterointerfacial properties of ε-Ge/InxGa1-xAs heterostructures grown on GaAs and Si substrates. Additionally, the influence of strain on MOS interfaces with Ge is examined, with specific application toward low-defect density ε-Ge MOS device design. Finally, vertical ε-Ge/InxGa1-xAs tunneling junctions are fabricated and characterized for the first time, demonstrating their viability for the continued development of next-generation low-power nanoelectronic devices utilizing the Ge/InxGa1-xAs material system. / Doctor of Philosophy / The aggressive scaling of transistor size in silicon-based complimentary metal-oxide-semiconductor technology has resulted in an exponential increase in integrated circuit (IC) computing power. Simultaneously, advances in materials science, transistor design, IC architecture, and microelectronics fabrication technologies have resulted in reduced IC operating power requirements. As a consequence, state-of-the-art microelectronic devices have computational capabilities exceeding those of the earliest super computers at a fraction of the demand in energy. Moreover, the low-cost, high-volume manufacturing of these microelectronic devices has resulted in their nigh-ubiquitous proliferation throughout all aspects of modern life. From social engagement to supply chain logistics, a vast web of interconnected microelectronic devices (i.e., the "Internet of Things") forms the information technology bedrock upon which 21st century society has been built. Hence, as progress in microelectronics and related fields continues to evolve, so too does their impact on an increasingly dependent world. Moore's Law, or the doubling of IC transistor density every two years, is the colloquialism used to describe the rapid advancement of the microelectronics industry over the past five decades. As mentioned earlier, parallel improvements in semiconductor technologies have spearheaded great technological change. Nevertheless, Moore's Law is rapidly approaching the physical limits of transistor scaling. Consequently, in order to continue improving IC (and therefore microelectronic device) performance, new innovations in materials and fabrication science, and transistor and IC designs are required. To that end, this research systematically investigates the material, optical, and electrical properties of novel semiconductor material systems combining elemental (e.g., Germanium) and compound (e.g., Gallium Arsenide) semiconductors. Additionally, alternative transistor design concepts are explored that leverage the unique properties of the aforementioned materials, with specific application to low-power microelectronics. Therefore, through a holistic approach towards semiconductor materials, devices, and circuit co-design, this work demonstrates, for the first time, novel transistor architectures suitable for the continued development of next-generation low-power, high-performance microelectronic devices.

We present fabrication of n-type organic field effect transistors (OFETs) using densely aligned array carbon nanotube (CNT) electrodes. The CNTs were aligned with a high linear density via dielectrophoresis (DEP) from an aqueous solution. In order to fabricate the CNT electrodes, aligned CNTs were cut by using electron beam lithography (EBL) and precise oxygen plasma etching. The n-type OFETs were fabricated in a bottom-contact configuration by depositing a thin film of C60 molecules between the CNT source and drain electrodes, and compared against a controlled C60 OFET with gold electrodes. The electron transport measurements of the OFETs using CNT electrodes show better transistor characteristics compared to OFETs using gold electrodes due to improved charge injection from densely aligned and open-ended nanotube tips.

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Gallium arsenide MESFETS require protective passivation at several steps in their fabrication. A common film used for device passivation is silicon nitride. This passivation film is deposited on gallium arsenide substrates by chemical vapor deposition techniques and possesses high intrinsic stress. The stresses arise from the difference in the gallium arsenide and silicon nitride material properties, such as coefficient of expansion, density, modulus, and deposition temperature. The stress has been shown to cause electrical performance shifts in GaAs MESFET structures due to the piezoelectric nature of the gallium arsenide lattice. This work develops a framework of mathematical models and experimental techniques by which the intrinsic stresses in the film and the GaAs substrate can be evaluated. Specifically, this work details the stress field and the electrical performance shifts in fully planarized self aligned gate GaAs MESFETS. The devices were 10 micron gate periphery FET devices with a 0.4 micron etched gate length. The test devices included both enhancement mode and depletion mode structures. The major contributors to the stress in GaAs devices was found to be the intrinsic stress effects of the silicon nitride passivation film. An externally applied stress, such as that applied to a package base that a typical GaAs device would be mounted into for actual service, was found to be insufficient to cause significant shifts in the device performance. The package body effectively reduces the transfer of stress to the device body and thereby minimizes the piezoelectric effect. The intrinsic stress effects are due to the deposition of the film itself. This intrinsic stress was found to have a significant effect on the device electrical characteristics. The stress was found to permanently shift the threshold voltage and current in 10 micron self aligned gate MESFETS. The shift was measured at 26 millivolts per 100 MPa film stress for depletion mode devices and 23 millivolts per 100 MPa for enhancement mode devices. For the maximum measured biaxial stress of -0.54 MPa in the gallium arsenide, the total measured shift was 140 millivolts. The level of shift is similar to that reported by earlier researchers. This piezoelectric shift has been modeled, with model predictions within 50/0 of the experimental values for the DFET devices and 11 % for the EFET devices. / Ph. D.

Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D. / The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion “smart” devices will be connected and “online” by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications.