In this research, Ni–NiOx–Cr and Ni–NiOx–ZnO–Cr metal-insulator-metal (MIM) junction based tunnel diodes have been investigated for the purpose of a wide-band detector. An MIM diode has a multitude of applications such as harmonic mixers, rectifiers, millimeter wave and infrared detectors. Femtosecond-fast electron transport in MIM tunnel diodes also makes them attractive for energy-harvesting devices. These applications require the tunnel diodes to have high current-asymmetry and non-linear current-voltage behavior at low applied voltages and high frequencies. Asymmetric and non-linear characteristics of Ni–NiOx-Cr MIM tunnel diodes were enhanced in this research by the addition of ZnO as a second insulator layer in the MIM junction to form metal-insulator-insulator-metal (MIIM) structure. Electrical characteristics were studied in a voltage range of for the single-insulator Ni–NiOx–Cr and double-insulator Ni–NiOx–ZnO–Cr tunnel diodes. Since the electrical characteristics of the diode are sensitive to material selection, material arrangement, thickness, deposition techniques and conditions, understanding the diode behavior with respect to these factors is crucial to developing a robust diode structure. Thus, ZnO insulator layer in MIIM junction was deposited by two different techniques: sputtering and atomic layer deposition (ALD). Also, the optical properties were characterized for the sputter deposited NiOx insulator layers by ellipsometry and the impact of annealing was explored for the NiOx optical properties. The Ni–NiOx–Cr MIM tunnel diodes provide low resistance but exhibit a low (~1) current-asymmetry. Asymmetry increased by an order of magnitude in case of Ni–NiOx–ZnO–Cr MIIM tunnel diode. The sensitivity of the MIM and MIIM diodes was 11 V-1 and 16 V-1, respectively. The results suggest that the MIIM diode can provide improved asymmetry at low voltages. The tunneling behavior of the device was also demonstrated in the 4-298K temperature range. It is hypothesized that the improved performance of the bilayer insulator diode is due to resonant tunneling enabled by the second insulator. Finally, the MIM and MIIM devices were investigated for wide-band detection up to 50GHz (RF) and 0.3THz (optical).

Le travail de recherche présenté dans ce manuscrit contribue à une étude générale de la susceptibilité électromagnétique (EM) d'un transistor MOS (Metal Oxide Semiconductor) dans une gamme de fréquences allant de 10 MHz à 1 GHz. Ce composant est destiné à un usage général pour des applications analogiques et numériques. Le but principal de ce travail est d'apporter une compréhension fine des mécanismes physiques mis en jeu au sein du composant lorsque ce dernier est soumis à une agression EM injectée en mode conduit au niveau de sa grille. Notre étude porte sur l'élaboration d'un modèle physique, essentiellement basé sur les variations de charges au sein du composant électronique. Cette approche permet à la fois de comprendre le fonctionnement nominal du transistor et la modification de son comportement lors d'un dysfonctionnement. En effet, la compréhension des mécanismes physiques mis en jeu est la base de la compréhension de la susceptibilité EM. Pour mettre en œuvre ce type d'approche, nous avons choisi d'étudier un type de susceptibilité correspondant à la modification de son point de fonctionnement sous agression EM. Cette modification du point de fonctionnement peut induire un dysfonctionnement du circuit dans lequel est implanté le transistor. Le phénomène physique à l'origine duquel les signaux parasites EM modifient le point de fonctionnement d'un composant électronique est le phénomène de redressement. Ce phénomène apparaît lorsqu'une distorsion est créée au sein du composant. C'est aussi pourquoi les non-linéarités du dispositif sont directement responsables de son observation. Ainsi, pour comprendre finement et physiquement l'effet induit par une agression EM, il est nécessaire de mettre en place une méthode d'étude. Celle-ci est basée sur une mesure des formes d'onde des courants à tous les accès du transistor. En effet, la visualisation de ces courants renseigne sur l'évolution des charges au sein de la structure. De plus, une telle mesure donne accès à une large palette d'observables (valeurs moyennes des courants, distorsions des courants, valeurs crêtes des courants, etc..). Dans un premier temps, les différentes mesures des formes d'onde des courants ont été réalisées lorsqu'une impulsion de tension était appliquée sur la grille du composant avec des temps de montée variables et choisis par rapport au temps de réponse du transistor. Cela nous a permis d'approfondir la compréhension du fonctionnement transitoire fort signal du MOSFET. Dans un second temps, nous avons mesuré les courants lors de l'application d'un signal EM à la grille du composant. En support à ces mesures nous avons utilisé deux outils de calcul : analytique et numérique. La méthode analytique permet la prédiction et l'identification des grandeurs du composant mises en jeu dans le mécanisme de la modification du comportement du transistor. La méthode numérique par simulation électrique permet, quant à elle, de prédire les effets de l'agression EM. Une étape de caractérisation statique et dynamique du composant a également été nécessaire pour enrichir la compréhension des phénomènes observés et fournir les entrées au modèle. / The research work presented here contributes to an overall study of the electromagnetic (EM) susceptibility of Metal Oxide Semiconductor Field Effect Transistors (MOSFET's), in a frequency range from 10 MHz to 1 GHz. This device is used for general purpose: analog and digital applications. The main aim of this study is to provide a detailed understanding of the physical mechanisms involved in the device when the Radio-Frequency (RF) interference is superimposed on the gate terminal. Our study focuses on the development of a physical model, based essentially on the charge variations within the electronic device. This approach allows to understand its behavior with and without the RF interference. Indeed, the knowledge of the involved physical mechanisms is the basic understanding of EM susceptibility. When RF interference is superimposed on the MOSFET terminals, various susceptibility effects take place depending on RF power level, frequency and the transistor operation region. Due to the nonlinearity of the MOS current-voltage characteristics, RF excitations cause distorted drain current waveform which leads to a bias point shift. This modification of the average drain current is called rectification effect. So we developed a method to clearly understand the effect induced by the EM interference. This method is based on the measurement of the currents waveforms to all of the transistor access. In fact, these currents waveforms measurements give us information on the charge variations within the electronic device. Moreover, such a measurement provides access to a wide range of current information (average values, distortion, peak values, etc.). Initially, the different currents waveforms measurements were made when a voltage ramp was applied to the device gate with variable rise time in respect to the transistor response time. This allowed us to understand the large signal transient response of the MOSFET. Secondly, we measured the currents waveforms when an EM interference was injected to the gate terminal. In support of these measurements we used two computation tools: analytical and numerical. The analytical method allows prediction and identification of the quantities of the device involved in the modification of transistor's behavior. The numerical method allows electrical simulation to predict the effects of EM aggression. A static and dynamic characterization of the component was also necessary to understand the observed phenomenon and provide data to the electrical model.

Built with nanomagnets, a spintronic device called the all-spin logic (ASL) device carries information with only spin currents, resulting in a low power supply--10 mV. This voltage is 100 times smaller than the conventional CMOS devices (usually 0.8~1V). The potential for improved energy efficiency made possible by the low operating voltage of ASL makes it one of the most promising devices among its post-CMOS competitors. The basic working principles of ASL device are introduced in this thesis and two complementary approaches to studying energy efficiency of computation are applied to a common set of ASL circuits: (1) a circuit simulation approach that provides efficiency estimates for specific ASL circuit realizations, and (2) a physical-information-theoretic approach that reveals fundamental efficiency bounds for ASL circuits as limited by irreversible information loss. The results of this study support the expectation that the energy efficiency of computation in ASL can far exceed that of CMOS. However, it also reveals that ASL efficiencies--shown to exceed fundamental limits by many orders of magnitude in the ASL implementations studied here--are unlikely to approach fundamental limits because of the unavoidable energetic overhead cost of maintaining spin currents.

Flexible Hybrid Electronics (FHEs) offer many advantages to the future of wearable technology. By combining the dynamic performance of conductive inks, and the functionality of ultra-thinned, traditional IC technology, new FHE devices allow for development of applications previously excluded by relying on a specific type of electronics technology. The characterization and reliability analysis of stretchable conductive inks paired with ultra-thin silicon die in theµm range was conducted. A silver based ink designed to be stretchable was screen printed on a TPU substrate and cured using box oven, conveyor convection oven, and photonic curing processes. Reliability tests were conducted including a tape test, crease test, wash test, and abrasion test. Optimization of each curing process resulted in all three methods’ ability to achieve the ink sheet resistance specification of <75mΩ/square/25µm. Reliability tests on the printing concluded that, if fully cured, all samples achieve similar reliability performance. Additionally, a series of 10 mm x 10 mm ultra-thin die were characterized using stylus profilometry and optical measurement in order to test the die quality and readiness for assembly. The die had been thinned from an initial thickness down of 600 µm to a target of 50 µm. A direct inverse relationship was shown between die thickness and die warpage, likely due to high levels of internal stress caused by the dicing and thinning process. Finally, an innovate pairing of serpentine copper clad traces on TPU was tested for reliability performance using traditional solder for die attachment.

Graphene electronics represent a developing field where many material properties and devices characteristics are still unknown. Researching several possible fabrication processes creates a fabrication process using resources found at Cal Poly a local industry sponsor. The project attempts to produce a graphene network in the shape of a fractal Sierpinski carpet. The fractal geometry proves that PDMS microfluidic channels produce the fine feature dimensions desired during graphene oxide deposit. Thermal reduction then reduces the graphene oxide into a purified state of graphene. Issues arise during thermal reduction because of excessive oxygen content in the furnace. The excess oxygen results in devices burning and additional oxidation of the gate contacts that prevents good electrical contact to the gates. Zero bias testing shows that the graphene oxide resistance decreases after thermal reduction, proving that thermal reduction of the devices occurs. Testing confirms a fabrication process producing graphene electronics; however, revision of processing steps, especially thermal reduction, should greatly improve the yield and functionality of the devices.

Vernier Tuned Distributed Bragg Reflector (VT-DBR) lasers have had great success in the field of Swept-Source Optical Coherence Tomography (SS-OCT) due to their continuous and nearly 40 nm wavelength tuning range in a single longitudinal mode. Fast sweeps allow for real time imaging with micrometer resolution at a distance of a few centimeters. While this laser has proven quite useful as a medical imaging tool via OCT, it has yet to similarly prove itself for general light detection and ranging (LIDAR) applications due to range limitations that arise from a finite laser coherence length. The goal of this thesis is to explore LIDAR applications for VT-DBR lasers and how to improve VT-DBR performance for LIDAR. In the scope of this work, LIDAR is laser imaging at tens or hundreds of meters with a resolution finer than 10cm. In order to achieve this kind of LIDAR performance with a VT-DBR laser, the laser must have a linewidth less than 1MHz over a tuning range of around 10GHz. This thesis outlines two methods towards this goal. The bulk of this work is dedicated to looking for and characterizing VT-DBR tuning paths with fundamentally narrow linewidth using microampere currents in both forward and reverse bias conditions. The second part of this thesis is a preliminary design of an optical frequency-locked loop to reduce laser phase noise, which subsequently reduces the laser linewidth. By tuning with small currents in the forward bias condition, nearly the entire range of laser wavelengths could be tuned to, but areas of narrow linewidth were both sparse and very sensitive to any change in bias. The reverse bias case showed limited but continuous tuning with increased reverse current magnitude. In this reverse biased photo-detector mode the laser exhibited narrower linewidth less than 15MHz, with the linewidth at intrinsically narrow levels when all three sections reverse biased. Also promising was a subset of reverse bias conditions that only used a variable resistance across a laser section with no externally applied bias. This resistance tuning method gave a tuning range of more than 7GHz while maintaining an intrinsically narrow linewidth. The optical frequency-locked loop was able to achieve DC frequency locking but unable to reduce laser linewidth. More work needs to be done to achieve enough phase noise reduction to see an appreciable reduction in linewidth.

Nanomagnetic devices are highly energy efficient and non-volatile. Because of these two attributes, they are potential replacements to many currently used information processing technologies, and they have already been implemented in many different applications. This dissertation covers a study of nanomagnetic devices and their applications in various technologies for information processing – from simulating and analyzing the mechanisms behind the operation of the devices, to experimental investigations encompassing magnetic film growth for device components to nanomagnetic device fabrication and measurement of their performance. Theoretical sections of this dissertation include simulation-based modeling of perpendicular magnetic anisotropy magnetic tunnel junctions (p-MTJ) and low energy barrier nanomagnets (LBM) – both important devices for magnetic device-based information processing. First, we propose and analyze a precessionally switched p-MTJ based memory cell where data is written without any on-chip magnetic field that dissipates energy as low as 7.1 fJ. Next, probabilistic (p-) bits implemented with low energy barrier nanomagnets (LBMs) are also analyzed through simulations, and plots show that the probability curves are not affected much by reasonable variations in either thickness or lateral dimensions of the magnetic layers. Experimental sections of this dissertation comprise device fabrication aspects from the basics of material deposition to the application-based demonstration of an extreme sub-wavelength electromagnetic antenna. Magnetic tunnel junctions for memory cells and low barrier nanomagnets for probabilistic computing, in particular, require ultrathin ferromagnetic layers of uniform thickness, and non-uniform growth or variations in layer thickness can cause failures or other problems. Considerable attention was focused on developing methodologies for uniform thin film growth. Lastly, micro- and nano-fabrication methods are used to build an extreme sub-wavelength electromagnetic antenna implemented with an array of magnetostrictive nanomagnets elastically coupled to a piezoelectric substrate. The 50 pW signal measured from the approximately 250,000-nanomagnet antenna sample was 10 dB above the noise floor.

This thesis describes an experimental study and modeling of the current-transconductance dependence of the ALD1106, ALD1107, and CD4007 arrays. The study tests the hypothesis that the I-gm dependence of these 7.8 µm to 10 µm MOSFETs conforms to the Advanced Compact Model (ACM). Results from performed measurements, however, do not support this expectation. Despite the relatively large length, both ALD1106 and ALD1107 show sufficiently pronounced ‘short-channel’ effects to render the ACM inadequate. As a byproduct of this effort, we confirmed the modified ACM equation. With an m factor of approximately 0.6, it captures the I-gm dependence with sub-28% maximum error and sub-10% average error. The paper also introduces several formulas and procedures for I-gm model extraction and tuning. These are not specific to the ALD transistor family and can apply to MOSFETs with different physical size and electrical performance.

A millimeter-wave (W-Band) down-converter for Phased Focal Plane Arrays (PFPAs) has been designed and fabricated using the IBM Silicon-Germanium (SiGe) BiCMOS 8HP process technology. The radio frequency (RF) input range of the down-converter chip is from 70 95GHz. The intermediate frequency (IF) range is from 5 30GHz. The local oscillator (LO) frequency is fixed at 65GHz. The down-converter chip has been designed to achieve a conversion gain greater than 20dB, a noise figure (NF) below 10dB and input return loss greater than 10dB. The chip also has novel LO circuitry facilitating LO feed-through among down-converters chips in parallel. This wide bandwidth down-converter will be part of millimeter-wave PFPA receiver designed and fabricated in collaboration with the University of Massachusetts-Amherst Department of Astronomy. This PFPA receiver will be installed on Green Bank Telescope (GMT) / Large millimeter wave telescope (LMT) in Q2 of 2014. This project is collaboration between the University of Massachusetts-Amherst (UMass), Brigham Young University (BYU) and National Radio Astronomy Observatory (NRAO). To the best of the author’s knowledge, this is first wide bandwidth down-converter at W-band to achieve this high gain and low noise figure among Si/SiGe based systems.

Optical Proximity Correction (OPC) is a part of a family of techniques called Resolution Enhancement Techniques (RET). These techniques are employed to increase the resolution of a lithography system and improve the quality of the printed pattern. The fidelity of the pattern is degraded due to the disparity between the wavelength of light used in optical lithography, and the required size of printed features. In order to improve the aerial image, the mask is modified. This process is called OPC, OPC is an iterative process where a mask shape is modified to decrease the disparity between the required and printed shapes. After each modification the chip is simulated again to quantify the effect of the change in the mask. Thus, lithography simulation is an integral part of OPC and a fast lithography simulator will definitely decrease the time required to perform OPC on an entire chip. A lithography simulator which uses wavelets to compute the aerial image has previously been developed. In this thesis I extensively modify this simulator in order to execute it on a Graphics Processing Unit (GPU). This leads to a lithography simulator that is considerably faster than other lithography simulators and when used in OPC will lead to drastically decreased runtimes. The other work presented in the proposal is a fast OPC tool which allows us to perform OPC on circuits faster than other tools. We further focus our attention on metrics like runtime, edge placement error and shot size and present schemes to improve these metrics.