In this thesis, we are concerned with content dissemination in mobile ad hoc networks. The scope of content dissemination is limited by network capacity, and sometimes the price to be paid for securing faster delivery. In the first part of the thesis, we address the issue of finding the maximum throughput that a mobile ad-hoc network can support. We have assumed that there is no price involved, and all nodes work as a team. The problem of determining the capacity region has long been known to be NP-hard even for stationary nodes. Mobility introduces an additional dimension of complexity because nodes now also have to decide when they should initiate route discovery. Since route discovery involves communication and computation overhead, it should not be invoked very often. On the other hand, mobility implies that routes are bound to become stale, resulting in sub-optimal performance if routes are not updated. We attempt to gain some understanding of these effects by considering a simple one-dimensional network model. The simplicity of our model allows us to use stochastic dynamic programming (SDP) to find the maximum possible network throughput with ideal routing and medium access control (MAC) scheduling. Using the optimal value as a benchmark, we also propose and evaluate the performance of a simple threshold-based heuristic. Unlike the optimal policy which requires considerable state information, the proposed heuristic is simple to implement and is not overly sensitive to the threshold value. We find empirical conditions for our heuristic to be near-optimal. Also, network scenarios when our heuristic does not perform very well are analyzed. We provide extensive numerical analysis and simulation results for different parameter settings of our model. Interestingly, we observe that in low density network the average throughput can first decrease with mobility, and then increase. This motivates us to study a mobile ad-hoc network when it is sparse and in a generalized environment, such as when movement of nodes is in a two-dimension plane. Due to sparseness, there are frequent disruptions in the connections and there may not be any end-to-end connection for delivery. The mobility of nodes may be used for carrying the forwarded message to the destination. This network is also known as a delay tolerant network. In the rest part of the thesis, we consider the relay nodes to be members of a group that charges a price for assisting in message transportation. First, we solve the problem of how to select first relay node when only one relay node can be chosen from a given number of groups. Next, we solve two problems, namely price-constrained delay minimization, and delay-constrained price optimization.

A novel controller termed as Experience Mapping based Prediction Controller (EMPC) is developed in this work. EMPC is developed utilizing the broad control concepts of human motor control (HMC). The concepts of HMC are utilized to develop the core concepts of EMPC for the control of ideal Type-1 LTI systems. The control accuracy of the developed concepts is studied and the mathematical stability criterion for the controller is developed. The applicability of EMPC for the control of real world problems is tested on a Permanent Magnet DC motor based position control system. 1. Novel learning methods are presented to form experience mapped knowledge-base (EMK) which is used for the creation of the forward and inverse models. 2. Control and Adaptation Techniques which overcome the presence of non idealities are developed using the inverse model. 3. Two separate techniques which utilize the forward model for improving the adaptation capabilities of EMPC are developed. 4. Two novel techniques are developed for the improvement of the tracking performance in terms of the accuracy and smoothness of tracking. These techniques are tested under various system conditions including large dynamic parameter changes on a simulation model and a practical setup. The performance of EMPC is compared against that of PID, MRAC and LQG controllers for all the proposed techniques and EMPC is found to perform significantly better under the various system conditions in terms of transient and steady state characteristics. Finally, the effectiveness of EMPC in stabilizing unstable systems using the concepts developed is tested on a practical Inverted Pendulum system. The problem of the simultaneous development of experiences and control of the system is addressed with the stabilizing problem. The proposed controller, EMPC provides an alternative approach for the existing control of systems without the requirement of an accurate system mathematical model. Its capability to learn by directly interacting with the system and adapt using experiences makes it an attractive alternative to other control techniques present in literature. Keywords: EMPC, Position Control, PMDC motors

Power distribution network (PDN) design was a non-existent entity during the early days of microprocessors due to the low frequency of operation. Once the switching frequencies of the microprocessors started moving towards and beyond MHz regions, the parasitic inductance of the PCB tracks and planes started playing an important role in determining the maximum voltage on a PDN. Voltage regulator module (VRM) sup-plies only the DC power for microprocessors. When the MOSFETs inside a processor switches, it consumes currents during transition time. If this current is not provided, the voltage on the supply rails can go below the specifications of the processor. For lower MHz processors few ceramic-capacitors known as ‘decoupling capacitors’ were connected between power and ground to provide this transient current demand. When the processor frequency increased beyond MHz, the number of capacitors also increased from few numbers to hundreds of them. Nowadays, the PDN is said to be comprising all components from VRM till the die location. It includes VRM, bulk capacitors, PCB power planes, capacitor mounting pads and vias, mount for the electronic package, package capacitors, die mount and internal die capacitance. So, the PDN has evolved into a very complex system over the years. A PDN should provide three distinct roles; 1) provide transient current required by the processor 2) act as a stable reference voltage for processor 3) filter out the noise currents injected by the processor. The first two are required for the correct operation of the processor. Third one is a requirement from analog or other sensitive circuits connected to the same PDN. If the noise exits the printed circuit board (PCB), it can result in conducted and radiated EMI, which can in turn result in failure of a product in EMC testing. Every PDN design starts with the calculation of a target impedance which is given as the ratio of maximum allowed ripple voltage to the maximum transient current required by the processor. The transient current is usually taken as half the average input current. The definition of target impedance assumes that the PDN is flat over the entire frequency of operation, which is true only for a resistive network. This is seldom true for a practical PDN, since it contains inductances and capacitances. Because of this, a practical PDN has an uneven impedance versus frequency envelope. Whenever two capacitors with different self resonant frequencies are connected in parallel, their equivalent impedance produces a pole between the self resonant frequencies known as antiresonance peaks. Because of this, a PDN will have phase angles associated with them. Also, these antiresonance peaks are energy reservoirs which will be excited during the normal operation of a processor by the varying currents. The transient current of a microprocessor is modeled as a gamma function, but for practical cases it can be approximated as triangular waveforms during the transition time which is normally 10% of the time period. Depending upon the micro-operations running inside the processor, the peak value of this waveform varies. This is filtered by the on-chip capacitors, package inductance and package capacitors. Due to power gating, clock gating, IO operations, matrix multiplications and magnetic memory readings the waveforms at the board will be like pulse type, and their widths are determined by these operations. In literatures, these two types of waveforms are used for PDN analysis, depending upon at which point the study is conducted. Chapter 1 introduces the need for PDN design and the main roles of a PDN. The issue of antiresonance is introduced from a PDN perspective. Different types of capacitors used on a PDN are discussed with their strengths and limitations. The general nature of the switching noise injected by a microprocessor is also discussed. This chapter discusses the thesis contributions, and the existing work related to the field. Chapter 2 introduces a new method to calculate the target impedance (Zt ) by including the phase angles of a PDN which is based on a maximum voltage calculation. This new Zt equals to conventional Zt for symmetrical triangular switching current waveforms. The value of new Zt is less than the conventional Zt for trapezoidal excitation patterns. By adding the resonance effects into this, a maximum voltage value is obtained in this chapter. The new method includes the maximum voltage produced on a PDN when multiple antiresonance peaks are present. Example simulations are provided for triangular and pulse type excitations. A measured input current wave-form for PIC16F677 microcontroller driving eight IO ports is provided to prove the assumption of pulse type waveforms. For triangular excitation waveform, the maximum voltage predicted based on the expression was ¡0.6153 V, and the simulated maximum voltage was found to be at ¡0.5412 V which is less than the predicted value. But the predicted value based on Zt method was 1.9845 V. This shows that the conventional as well as the new target impedance method leads to over estimating the maximum voltage in certain cases. This is because most of the harmonics are falling on the minimum impedance values on a PDN. If the PDN envelope is changed by temperature and component tolerances, the maximum voltage can vary. So the best option is to design with the target impedance method. When pulse current excitation was studied for a particular PDN, the maximum voltage produced was -139.39 mV. The target impedance method produced a value of -100.24 mV. The maximum voltage predicted by the equation was -237 mV. So this shows that some times the conventional target impedance method leads to under estimating the PDN voltage. From the studies, it is shown that the time domain analysis is as important as frequency domain analysis. Another important observation is that the antiresonance peaks on a PDN should be damped both in number and peak value. Chapter 3 studies the antiresonance peak suppression methods for general cases. As discussed earlier, the antiresonance peaks are produced when two capacitors with different self resonant frequencies are connected in parallel. This chapter studies the effect of magnetic coupling between the mounting loops of two capacitors in parallel. The mounting loop area contribute to the parasitic inductance of a capacitor, and it is the major contributing factor to it. Other contributing factors are equivalent series inductance (ESL) and plane spreading inductance. The ESL depends on the size and on how the internal plates of the capacitors are formed. The spreading inductance is the inductance contributed by the parts of the planes connecting the capacitor connector vias to the die connections or to other capacitor vias. If the power and ground planes are closer, the spreading inductance is lower. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The inductance contributed by the mounted area of the capacitor is known as mounting inductance. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The dependencies of various circuit parameters on antiresonance peak are studied using circuit theory. A general condition for damping the antiresonance is formulated. The antiresonance peak reduces with Q factor. The conventional critical condition for antiresonance peak damping needs modification when magnetic coupling is present between the mounting loops of two parallel unequal value capacitors. By varying the connection geometry it is possible to obtain negative and positive coupling coefficients. The connection geometries to obtain these two are shown. An example is shown for positive and negative coupling coefficient cases with simulation and experimental results. For the example discussed, RC Æ 32 - for k Æ Å0.6 and RC Æ 64 - for k Æ ¡0.6, where RC is the critical damping value and k is the magnetic coupling coefficient between the two mounting loops. The reason for this is that, the antiresonance peak impedance value is higher for negative coupling coefficient case than that for positive coupling coefficient case. Above the self resonant frequencies of both the capacitors, the equivalent impedance of the parallel capacitors become inductive. This case is studied with two equal value capacitors in parallel. It is shown that the equivalent inductance is lower for negative coupling coefficient case as compared to positive coupling coefficient case. An example is provided with simulation and experimental results. In the experimental results, parasitic inductance is observed to be 2.6 times lower for negative coupling coefficient case than that for positive coupling coefficient case. When equal value capacitors are connected in parallel, it is advantageous to use a negative coupling geometry due to this. Chapter 4 introduces a new method to damp the antiresonance peak using a magnet-ically coupled resistive loop. Reducing the Q factor is an option to suppress the peak. In this new method, the Q factor reduction is achieved by introducing losses by mag-netically coupling a resistive loop. The proposed circuit is analyzed with circuit-theory, and governing equations are obtained. The optimum value of resistance for achieving maximum damping is obtained through analysis. Simulation and experimental results are shown to validate the theory. From the experimental results approximately 247 times reduction in antiresonance peak is observed with the proposed method. Effectiveness of the new method is limited by the magnetic coupling coefficient between the two mounting loops of capacitors. The method can be further improved if the coupling coefficient can be increased at the antiresonance frequency. Chapter 5 focuses on the third objective of a PDN, that is to reduce the noise injected by the microprocessor. A new method is proposed to reduce the conducted noise from a microprocessor with switched super capacitors. The conventional switched capacitor filters are based on the concept that the flying capacitor switching at high frequency looks like a resistor at low frequency. So for using at audio frequencies the flying capacitors were switching at MHz frequencies. In this chapter the opposite of this scenario is studied; the flying capacitors are the energy storage elements of a switched capacitor converter and they switch at lower frequencies as compared to the noise frequencies. Two basic circuits (1:1 voltage conversion ratio) providing noise isolation were discussed. They have distinct steady state input current waveforms and are explained with PSPICE simulations. The inrush current through switches are capable of destroying them in a practical implementation. A practical solution was proposed using PMOS-PNP pair. The self introduced switching noise of the converter is lower when switching frequency is low and turn ON-OFF time is higher. If power metal oxide semiconductor field effect transistor (MOSFET)s are used, the turn ON and turn OFF are slow. The switching frequency can be lowered based on the voltage drop power loss. The governing equations were formulated and simulated. It is found that the switching frequency can be lowered by increasing the capacitance value without affecting the voltage drop and power loss. From the equations, it is found that the design parameters have a cyclic dependency. Noise can short through the parasitic capacitance of the switches. Two circuits were proposed to improve the noise isolation: 1) T switch 2) ¦ switch. Of these, the ¦ switch has the higher measured transfer impedance. Experimental results showed a noise reduction of (40-20) dB for the conducted frequency range of 150 kHz - 30 MHz with the proposed 1:1 switched capacitor converter. One possible improvement of this method is to combine the noise isolation with an existing switched capacitor converter (SCC) topology. The discussed example had a switching frequency of 700 Hz, and it is shown that this can isolate the switching noise in kHz and MHz regions. In a PDN there are antiresonance peaks in kHz regions. If the proposed circuit is kept close to a microprocessor, it can reduce the excitation currents of these low frequency antiresonance peaks. Chapter 6 concludes the thesis by stating the major contributions and applications of the concepts introduced in the thesis. This chapter also discusses the future scope of these concepts.

In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally. The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The realization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc. However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transistors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the electronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood. In this work, we first develop the geometrically optimized atomistic models of the 2H-1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geometries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries. Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain). Next, using first principles based quantum transport calculations we demonstrate that due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values. Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis. The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.

This thesis addresses the problem of building a Cognitive Radio that has the ability to interact with human users in a better way by making use of Quality of Experience (QoE) as its basis and marshalling its resources optimally around the user. Salient activities of this thesis include: Analysis of CR leads to the definition of its basic functional blocks such as cognition, learning and adaptation of radio behaviour in a multi-disciplinary manner. CR tracts signal processing for radio and sensors, cognitive and behavioural psychology for user intelligence, machine learning and AI for decision systems and optimization etc. Therefore it provides a rich, fertile area to make lateral connections across diverse helds. This thesis proposes a broad definition for CR (called as Unifed Cognitive Radio) inspired by key foundation works described in literature. Besides, it also describes its functionality and its ecosystem. Taking cue from the definition of UCR, this thesis proposes architectural frame-works for various sub-systems. Also their design and implementation is achieved with the aid of a comprehensive tested setup and is tested using realistic scenarios. Builds a set of intelligent decision systems that help to achieve the set goal. This involves various design decisions with a set of diverse algorithms from the world of signal processing, machine learning and articial intelligence. Transitioning disparate small functional entities (mostly built around experiments) into an integrated system that works in real-world environment is the key aspect of this thesis. It is definitely a challenging task. Therefore, starting from deterring the architectural reference frameworks for realizing various sub-systems of UCR to an evaluation based on integrated scenario, this being an important final step constitutes a sign cant amount of work. Analysis and implementation of the integrated system to meet the desired end functionality - QoE centricity of the CR system to satisfy the needs of the end user better is the contribution of this thesis

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

Wheeled systems are energy efficient on prepared surfaces like roads and tracks. Legged systems are capable of traversing different terrains but can be lossy. At low speeds and on off-road surfaces, legged systems using dynamic walking can be energy efficient. Towards this objective, the dynamics of the walker needs to be modelled and controlled. In addition, the braking and ground impact losses need to be minimized. This thesis presents analysis and experiments on the dynamics and control of a rimless-spoked-wheel based mobile robot (Chatur ∗) that belongs to a category between wheeled and legged systems. This rolling rimless wheel is effectively a 2D dynamic walker that serves as a platform for investigating the dynamics and energetics of inverted pendulum walking with constant step angle. A pulsed actuation torque is proposed for the system resulting in four torque regimes defined by the ratio of energy losses to available actuator torque. Five physical constraints that impose fundamental limits on the choice of operating points of a generic inverted pendulum walker are expounded and a method for locating optimal operating points is discussed. Chatur’s hardware design is elaborated and a control topology is proposed for pulsed actuation of the dual brushless dc (BLDC) motor driven platform with wheel synchronization. Various actuator torque profiles can be used to achieve dynamic ‘walking’ in a hub-actuated rimless wheel. The proposed pulsed actuation torque gives rise to four torque regimes that achieve sustained walking and a fifth regime where the walker keeps slowing down with each step. The regimes can be identified based on the fraction of stance phase for which the actuator is energized. Theoretical analysis and experimental results are presented. A simple closed-form analytical solution, using hyperbolic functions, is proposed for the stance phase inverted pendulum dynamics considering planar motion. Ground impacts are assumed to cause abrupt drop in velocity. A constant braking torque that lumps together the effect of several loss phenomena is also considered. Based on whether the CoM is rising or falling and whether or not there is an actuating torque, a stance phase can have four types of sub-phases — actuated rise, unactuated rise, actuated fall, unactuated fall. These are concatenated in four different ways to form repeating cycles yielding the four regimes. The experimental set-up is a fixed step-angle walker constructed using two synchronized adjacent rimless wheels independently actuated at the hub. Varying the magnitude and duty ratio of the torque pulse, the four proposed regimes are experimentally shown. The mechanical power consumption and cost of transport are computed from measured motor currents for different average forward speeds. Videos of the walks are also taken. The space of operating points for an inverted pendulum based bipedal dynamic walker in terms of constraints and optimality is investigated. The operating point of the walker can be specified by the combination of initial mid-stance velocity (v0) and step angle (φm) chosen for a given walk. Not all operating points lead to a realizable steady-state gait. Using basic mechanics, a framework of physical constraints that limit the choice of operating points is proposed. The constraint lines thus obtained delimit the valid region of operation of the walker in the v0–φm plane. Within this allowable region, sub-regions that result in various regimes of walking are identified. A given average forward velocity vx,avg can be achieved by several combinations of v0 and φm. Only one of these combinations results in the minimum mechanical power consumption and can be considered the opti-mum operating point for the given vx,avg. A method is proposed for obtaining this optimal operating point based on tangency of the power and velocity contours. Putting together all such operating points for various vx,avg, a family of optimum operating points, called the optimal locus, is obtained. For the energy loss and internal energy models chosen, the optimal locus obtained has a largely constant step angle with increasing speed but tapers off at non-dimensional speeds close to unity. Thus, choosing the right step angle and keeping it fixed over a broad range of speeds could lead to an inverted pendulum walker that is close to optimal from a mechanical energy perspective. The complete hardware design for Chatur and the caveats associated with reliable performance of the mechanical and electrical subsystems are elaborated. In order to en-sure lateral stability, the system uses two contralateral wheels each driven by a separate BLDC hub motor. From a motor drive perspective, the mechanical load belongs to a unique class of dynamic loads whose reflected torque has a characteristic cyclic varia-tion that repeats several times within a mechanical revolution. The proposed control topology has two hierarchical levels, an inner loop for torque control of BLDC motor implemented using a standard proportional-integral controller, and an outer loop for torque reference generation that uses the information on the ground impact instants and the motor position feedback. Ground impacts of the spokes are detected by an accelerometer to initiate the application of torque. The torque pulse magnitude can be set internally or by a manual operator via radio control. The pulse duration is programmable and enables attainment of various torque regimes at different steady state speeds. The wheels are synchronized so that corresponding spokes on both wheels move in unison. This is achieved by including a wheel synchronization loop that compensates for any lag between the wheels. Lag is detected based on number of sector changes in the hall-effect position sensor data received from both motors. An improved BLDC motor drive is developed wherein non-commutating current feedback is used to reduce current spikes during sector transitions. Experimental waveforms for controller validation are shown.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

Achieving high computation efficiency, in terms of Cycles per Instruction (CPI), for high-performance computing kernels is an interesting and challenging research area. Dense Linear Algebra (DLA) computation is a representative high-performance computing ap- plication, which is used, for example, in LU and QR factorizations. Unfortunately, mod- ern off-the-shelf microprocessors fall significantly short of achieving theoretical lower bound in CPI for high performance computing applications. In this thesis, we perform an in-depth analysis of the available parallelisms and propose suitable algorithmic and architectural variation to significantly improve the computation efficiency. There are two standard approaches for improving the computation effficiency, first, to perform application-specific architecture customization and second, to do algorithmic tuning. In the same manner, we first perform a graph-based analysis of selected DLA kernels. From the various forms of parallelism, thus identified, we design a custom processing element for improving the CPI. The processing elements are used as building blocks for a commercially available Coarse-Grained Reconfigurable Architecture (CGRA). By per- forming detailed experiments on a synthesized CGRA implementation, we demonstrate that our proposed algorithmic and architectural variations are able to achieve lower CPI compared to off-the-shelf microprocessors. We also benchmark against state-of-the-art custom implementations to report higher energy-performance-area product. DLA computations are encountered in many engineering and scientific computing ap- plications ranging from Computational Fluid Dynamics (CFD) to Eigenvalue problem. Traditionally, these applications are written in highly tuned High Performance Comput- ing (HPC) software packages like Linear Algebra Package (LAPACK), and/or Scalable Linear Algebra Package (ScaLAPACK). The basic building block for these packages is Ba- sic Linear Algebra Subprograms (BLAS). Algorithms pertaining LAPACK/ScaLAPACK are written in-terms of BLAS to achieve high throughput. Despite extensive intellectual efforts in development and tuning of these packages, there still exists a scope for fur- ther tuning in this packages. In this thesis, we revisit most prominent and widely used compute bound algorithms like GMM for further exploitation of Instruction Level Parallelism (ILP). We further look into LU and QR factorizations for generalizations and exhibit higher ILP in these algorithms. We first accelerate sequential performance of the algorithms in BLAS and LAPACK and then focus on the parallel realization of these algorithms. Major contributions in the algorithmic tuning in this thesis are as follows: Algorithms: We present graph based analysis of General Matrix Multiplication (GMM) and discuss different types of parallelisms available in GMM We present analysis of Givens Rotation based QR factorization where we improve GR and derive Column-wise GR (CGR) that can annihilate multiple elements of a column of a matrix simultaneously. We show that the multiplications in CGR are lower than GR We generalize CGR further and derive Generalized GR (GGR) that can annihilate multiple elements of the columns of a matrix simultaneously. We show that the parallelism exhibited by GGR is much higher than GR and Householder Transform (HT) We extend generalizations to Square root Free GR (also knows as Fast Givens Rotation) and Square root and Division Free GR (SDFG) and derive Column-wise Fast Givens, and Column-wise SDFG . We also extend generalization for complex matrices and derive Complex Column-wise Givens Rotation Coarse-grained Recon gurable Architectures (CGRAs) have gained popularity in the last decade due to their power and area efficiency. Furthermore, CGRAs like REDEFINE also exhibit support for domain customizations. REDEFINE is an array of Tiles where each Tile consists of a Compute Element and a Router. The Routers are responsible for on-chip communication, while Compute Elements in the REDEFINE can be domain customized to accelerate the applications pertaining to the domain of interest. In this thesis, we consider REDEFINE base architecture as a starting point and we design Processing Element (PE) that can execute algorithms in BLAS and LAPACK efficiently. We perform several architectural enhancements in the PE to approach lower bound of the CPI. For parallel realization of BLAS and LAPACK, we attach this PE to the Router of REDEFINE. We achieve better area and power performance compared to the yesteryear customized architecture for DLA. Major contributions in architecture in this thesis are as follows: Architecture: We present design of a PE for acceleration of GMM which is a Level-3 BLAS operation We methodically enhance the PE with different features for improvement in the performance of GMM For efficient realization of Linear Algebra Package (LAPACK), we use PE that can efficiently execute GMM and show better performance For further acceleration of LU and QR factorizations in LAPACK, we identify macro operations encountered in LU and QR factorizations, and realize them on a reconfigurable data-path resulting in 25-30% lower run-time

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.