Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Daniel F. Baldwin. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M.S. in mechanical engineering)--Washington State University, December 2006. / Includes bibliographical references (p. 49).

Thesis (Ph. D.)--Mechanical Engineering, Georgia Institute of Technology, 2006. / Qu, Jianmin, Committee Chair ; Baldwin, Daniel, Committee Member ; Wong, C. P., Committee Member ; Sitaraman, Suresh, Committee Member ; Jacob, Karl, Committee Member.

The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality.

M.Ing. / Power electronic systems are often treated purely as electronic circuits. This results in manufactured systems that are electrically functional but not optimised in terms of packaging, temperature or volume. This, in turn, results in low power densities. The objective of this work is to investigate how a power converter should be built to obtain a high power density while operating at high ambient temperatures. In doing so, the parameters affecting the converter volume and thus the power density are identified. In this work, a case study is considered, comprising a DC/DC converter operating in the automotive environment. The specifications for the DC/DC converter identify the power density and high temperature operation as the primary design objectives. The DC/DC converter is implemented in the new dual voltage systems implemented in ultra-modern automobiles. An unconventional converter structure is proposed to meet the electrical and thermal specifications. The converter structure is divided into two sections, namely the active and passive components. The two components share a combined cooling structure. Each of the components is analysed fundamentally and with simulation packages on both an electrical and thermal level. The active and passive components are implemented with material technologies such as open die semiconductors on DCB substrates and high density planar inductors with specially designed cooling structures. The two components take advantage of the thermal performance of the different manufacturing technologies. The complete converter structure is implemented and evaluated both electrically and thermally. The converter structure achieves a power density of 170W/in3 while operating with a coolant temperature of 85°C. Based on the case study, techniques are developed and suggestions are made that will result in the power density and the operating temperature of the converter structure being increased. These suggestions can also be used and implemented in the design and development of any high power density and high operating temperature structure.

Current trends in electronics are toward the use of reduced voltages. In the past, 5 V and higher voltages have been the standard, however, currently, 3.3V and 2.5V circuits are becoming increasingly common. While the operating voltage is decreasing, electronic systems are becoming more complex. The net result is that in many, cases, the current required by the next generation of electronics will be far greater than in the past. These increased currents and low voltages pose dramatic problems for designers not the least of which is the effect of electronic packaging and circuit implementation on the overall power supply performance. In addition, for many applications, space and weight are at a premium and converters are needed to power low voltage circuit assemblies that are highly efficient, low in weight, and small in total height and foot print. This dissertation addresses these trends and needs through the design, fabrication and evaluation of a 3.3V DC/DC converter. Designs of 3.3V, 2.5V, and 1.5V are presented and evaluated while a 3.3V, 100 watt converter with a power density of 157 watts/in³ has been fabricated and evaluated in a miniature form. This converter utilizes a implementation strategy developed by the author which was selected due to its ability to handle the current levels required and its compact size. Specific contributions of this work include: • Analysis of the effects of packaging on low voltage high current converters in order to provide a guideline for converter implementation. This analysis has been performed for 3.3 V, 2.5 V, and 1.5 V designs, respectively. • Development of high efficiency 2.5 V, 100 watt and 1.5 V, 75 watt designs based on previously reported half bridge topologies. • Development of a packaging strategy which allows the fabrication of low voltage compact converters with high efficiency. A 3.3 V converter has been fabricated and with the simulated data validated these experimental results. For very low (less than 50 watts and / or less than 10 amps) and high power levels (hundreds of amps or kilowatts), the implementation strategy is normally clear; PCB/IMS, and DBC respectively. However, for applications in the middle range of power or current level, the optimum implementation is often unclear. The question that this work seeks to answer is under what conditions are different implementation schemes most suitable. / Ph. D.

No description available.

Underfill material is a special colloidal dispersion system with silicon dioxide particles in the organic liquid. It is used to improve the reliability of integrated circuits (IC) packaging in the microelectronics. In order to successfully synthesize the nanocomposite underfill meeting the requirements of the chip package, it is necessary to have a fundamental understanding about the particle stability in the non-aqueous liquid and the relationship between materials properties and interphase structure in the composite. The results of this thesis contribute to the knowledge of colloidal dispersion of nanoparticles in organic liquid by systematically investigating the effects of particle size, particle surface chemistry and surface tension, and liquid medium polarity upon the rheological and thermal mechanical properties of underfill materials. The relaxation and dielectric properties studies indicate that the polymer molecular chain motion and polarization in the interphase region can strongly influence the material properties of nanocomposite, and so a good interaction between particle and polymer matrix is key. With this study, a potential nanocomposite underfill can be synthesized with low viscosity, low thermal expansion, and high glass transition temperature. The excellent transmittance of nanoparticles leads to further investigation of their ability as reinforcing filler in the photo-curable polymer.

No description available.