OpenGL ES 2.0 is the newest 3D graphics technology for hand-held devices established by Khronos. Users need a shading language compiler and a graphics card which is supportive for OpenGL ES 2.0 to develop their application on OpenGL ES 2.0. Without a graphcis processing unit and a corresponding compiler, one can not develop a 3D graphics application based on OpenGL ES 2.0. In order to solve these problems, we proposed an emulator for OpenGL ES 2.0 based on C-language compiler. The proposed emulator applies C-language compiler and CPU to fulfill the specification of OpenGL ES 2.0. With the proposed emulator, application developers can develop a 3D graphics application for OpenGL ES 2.0 without a specific hardware and a corresponding compiler and hardware designers also can compare and debug when designing their own graphics processing unit.

With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on current multi-core architectures. The multi-core system has a brilliant performance in executing multi-threaded applications, but this system could not gain any performance in single-threaded applications. This paper proposes a multi-core architecture for enhancing single-threaded performance in embedded system, and focuses on four points: 1. Construct a simple out-of-order execution core. 2. Design a dynamically scheduled instruction analyzer. 3. Design a mechanism for sharing operands between two cores. 4. Design a mechanism for committing instructions synchronously between two cores. The architecture of each core is single-issue out-of-order instruction pipe. First, instruction analyzer will fetch instructions and generate instruction dependence tags by detecting the dependencies among the fetched instructions, then schedule instructions dynamically and dispatch to the cores. In the core, instructions can know where to get required operands according to the information of instruction tags, this mechanism enables data can be shared between two cores. Instructions are executed by data-driven approach, but in-order complete to maintain the correctness of the program order. Based on ARM instruction set, this paper tries to explore ways to achieve interaction control mechanisms between two cores and to accelerate a single-thread in the dual-core architecture. We write a simulation model of the proposed architecture in C language as our trace-driven simulation framework and the MediaBench suite is selected for the experiments. According simulation result, the architecture can obtain average 40% performance speedup comparing to the five-stage pipelined architecture.

Roadway illumination is a vital component of safety while driving during the night. There are regulations in place to ensure all publicly maintained roads are properly lit, but the validation process is too time consuming, costly, and dangerous for adequate data collection studies. The work in this thesis is aimed toward remedying this problem by creating an Advanced Lighting Measurement System (ALMS) capable of recording illumination readings while traveling at normal driving speeds. This solution is based on the Arduino Uno development board, a cost effective yet powerful embedded platform. This thesis involves collecting data along 100 centerline miles of Florida roadways and converting the resulting illumination readings into GIS format, allowing them to be included in the roadway database of the Florida Department of Transportation (FDOT). By including this data FDOT will be able to repair poorly lit corridors and will be aware of possible safety concerns. The illumination values recorded by the ALMS have been validated and verified as an accurate replacement for conventional lighting measurement system.

MP3, or MPEG-1 Layer 3, is the most widely-used format for storing compressed audio. MP3 is more advantageous than uncompressed audio (PCM), offering a much smaller size but without a noticeable loss in audio quality. This report will demonstrate decoding and playback of MP3 audio using a TLL5000 FPGA board. / text

In order to maximize operating time of an industrial machine and minimize stand-by time, service time and operating costs, a diagnostic system can be a useful tool. Diagnostic systems employ information already available in a machine’s control system (such as control signals, system state, sensor readings and so forth) to perform intelligent fault detection and localisation, and predict future faults and service needs. CC Systems develops advanced electronics and control systems for industrial machines and vehicles operating in rough environments. One of their products is a diagnostic platform called Diagnostic Runtime Engine (DRE), supplying the customer with a tool for building a diagnostic system. The platform offers supervision of the control system. Actions are performed when it detects a possible fault or indication of a potential future fault. An action could be for example the creation of an alarm. The DRE, as designed today, only works together with a control system running in an environment called CoDeSys. In this master thesis a new architecture of the platform is presented, with the objective to make the platform compatible with an arbitrary control system. A prototype is implemented to prove the concept of the suggested architecture model. A number of different standard diagnostic blocks, used for building the diagnostic system, are also suggested with the objective to make it easier for the user to employ the DRE. A proposition of how development with the diagnostic platform can proceed beyond this thesis is also presented. / För att maximera drifttid hos en industriell maskin och minimera driftskostnader samt standby- och service-tid, kan ett diagnostiksystem användas. Ett sådant system använder sig av information som redan finns tillgänglig i maskinens styrsystem (så som styrsignaler, tillstånd, sensorvärden och så vidare) för att utföra feldetektering och fellokalisering samt analys av möjliga framtida feltillstånd och servicebehov. CC Systems utvecklar avancerade elektronikkomponenter och styrsystem för industriella maskiner och fordon. En av deras produkter är en diagnostikplattform, Diagnostic Runtime Engine (DRE), som erbjuder ett verktyg för att bygga upp ett diagnostiksystem. Plattformen möjliggör övervakning av styrsystemet, och detektion av ett nuvarande feltillstånd eller möjligt framtida feltillstånd leder till att en handling utförs. En handling kan till exempel vara att ett alarm skapas. Diagnostikplattformen, som den är gjord idag, fungerar bara tillsammans med ett styrsystem som är implementerat i utvecklingsmiljön CoDeSys. I detta examensarbete presenteras en ny arkitektur på plattformen som möjliggör användande tillsammans med ett godtyckligt styrsystem. En prototyp är implementerad för att visa att den föreslagna arkitekturmodellen fungerar i praktiken. Dessutom är ett antal standard-diagnostikblock, som används då ett diagnostiksystem byggs upp, föreslagna. Standardblocken har till syfte att underlätta användandet av diagnostikplattformen. Ett förslag för hur DRE kan byggas om och utvecklas i framtiden är också presenterat.

To make a camera more user friendly or let it operate without an user the camera objective needs to be able to put thecamera lens in focus. This functionality requires a motor of some sort, due to its many benefits the ultrasonic motor is apreferred choice. The motor requires a driving circuit to produce the appropriate signals and this is what this thesis is about.Themain difficulty that needs to be considered is the fact that the ultrasonic motor is highly non-linear.This paper will give a brief walk through of how the ultrasonic motor works,its pros and cons and how to control it. How thedriving circuit is designed and what role the various components fills. The regulator is implemented in C-code and runs on amicro processor while the actual signal generation is done on a CPLD. The report ends with a few suggestions of how toimprove the system should the presented solution not perform at a satisfactory level.

This thesis describes a project to create a hardware based 3D interior scanner. This was based on a previous project that created a scanner optimised for interior conditions, using structured light triangulation. The original project referred to as the Mark-I scanner, performed its control and processing on a PC and the primary goal of this project was to re-implement this system using hardware, making the scanner more portable and simpler to use. The Mark-I system required a specialised camera which had an unusually high noise associated with it, so a secondary goal was to investigate whether this camera could be replaced with a superior model or this noise corrected. A Mark-II scanner system was created using FPGA processing and control implemented in the VHDL language. This read from a CMOS camera, controlled the system's motor and laser, generated 3D points and communicated with users. A suitable camera was not found and the Mark-I scanners camera was found to have been damaged and become unusable, so a simulation environment was constructed that simulated the operation of the scanner, created 3D images for it to process, and tested its results. Chapter 1 of this thesis outlines the goals of this pro ject and describes the Mark-I system. Chapter 2 describes the theory and properties of the Mark-I system, and chapter 3 describes the work undertaken to replace the scanner's sensor. Chapter 4 describes the system created to interface to CMOS sensors, and chapter 5 outlines the theory involved in calculating 3D points using structured light triangulation. The final hardware scanner, and the simulation system used to test it, are then described in chapter 6.

Recently, various special purpose processors have been developed and are frequently being used for different specialized tasks. Prominent among these are the communication processors, which are generally used within an embedded system environment. Such processors can run relatively advanced and general purpose operating systems such as uCLinux, which is a freely available embedded Linux distribution. In this work, a prototype SoHo (Small office / Home office) router is designed and implemented using Motorola MCF5272 as the core communication processor and uCLinux as the operating system. The implementation relies purely on the existing hardware resources of an available development board and the publicly available open source utilities of uCLinux. The overall development process provides an embedded system implementation and configuration example.

Real-time embedded systems (RTESs) have been widely used in modern society. And it is also very common to find them in safety and security critical applications, such as transportation and medical equipment. There are, usually, several constraints imposed on a RTES, for example, timing, resource, energy, and performance, which must be satisfied simultaneously. This makes the design of such systems a difficult problem. More recently, the security of RTESs emerges as a major design concern, as more and more attacks have been reported. However, RTES security, as a parameter to be considered during the design process, has been overlooked in the past. This thesis approaches the design of secure RTESs focusing on aspects that are particularly important in the context of RTES, such as communication confidentiality and side-channel attack resistance. Several techniques are presented in this thesis for designing secure RTESs, including hardware/software co-design techniques for communication confidentiality on distributed platforms, a global framework for secure multi-mode real-time systems, and a scheduling policy for thwarting differential power analysis attacks.  All the proposed solutions have been extensively evaluated in a large amount of experiments, including two real-life case studies, which demonstrate the efficiency of the presented techniques.

Made available in DSpace on 2014-06-12T15:52:55Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / Nos últimos anos, a redução do consumo de energia das aplicações dos sistemas embarcados tem recebido uma grande atenção da comunidade científica, visto que, como o tempo de resposta e o baixo consumo de energia são requisitos conflitantes, esses estudos tornam-se altamente necessários. Nesse contexto, é proposta uma metodologia aplicada nas fases iniciais de projeto para dar suporte às decisões relativas ao consumo de energia e ao desempenho das aplicações desses dispositivos embarcados. Al´em disso, esse trabalho propõe modelos temporizados de eventos discretos que são avaliados através de uma metodologia de simulção estocástica com o objetivo de representar diferentes cenários dos sistemas com facilidade. Dessa forma, para cada cenário ´e preciso decidir o n´umero máximo de simulações e o tamanho de cada rodada da simulação, onde ambos os fatores podem impactar no desempenho para se obter tais estimativas. Essa metodologia considera também, um modelo intermediário que representa a descrição do comportamento do sistema e, é através desse modelo que cenários são analisados. Esse modelo intermediário ´e baseado em redes de Petri coloridas temporizadas que permitem não somente a anáise do software, mas também fornece suporte a um conjunto de métodos bem estabelecidos para verificações de propriedades. É nesse contexto que o software, ALUPAS, responsável por estimar o consumo de energia e o tempo de execução dos sistemas embarcados é apresentado. Por fim, um caso de estudo real, assim como tamb´em, exemplos customizados são apresentados com a finalidade de mostrar a aplicabilidade desse trabalho, onde usuários não especializados não precisam interagir diretamente com o formalismo de redes de Petri.