L'archivage de données industrielles est un problème complexe : il s'agit de stocker un grand nombre de données sur plusieurs décennies, tout en supportant la charge des insertions temps réel et des requêtes d'extraction et d'analyse. Pour ce type d'application, des produits « de niche » se sont spécialisés pour ce segment du marché : les progiciels d'historisation. Il s'agit de solutions propriétaires avec des coûts de licence de l'ordre de plusieurs dizaines de milliers d'euros, et dont le fonctionnement interne n'est pas dévoilé. Nous avons donc dans un premier temps mis en évidence les spécificités de ces progiciels d'historisation, tant au niveau des fonctionnalités que des performances. Néanmoins, l'archivage de données industrielles peut s'appliquer à des contexte très différents. L'IGCBox par exemple est un mini PC industriel utilisant MySQL pour l'archivage à court terme des données de production des centrales hydrauliques d'EDF. Ce matériel présente quelques spécificités, la principale étant son système de mémoire non volatile basé uniquement sur la technologie flash, pour sa fiabilité importante en milieu industriel et sa faible consommation d'énergie. Les SGBD possèdent pour des raisons historiques de nombreuses optimisations spécifiques aux disques durs, et le manque d'optimisation adaptée aux mémoires flash peut dégrader significativement les performances. Le choix de ce type de mémoire a donc eu des répercussions notables sur les performances pour l'insertion, avec une dégradation importante par rapport aux disques durs. Nous avons donc proposé Chronos, un SGBD dédié à l'historisation de données sur mémoires flash. Pour cela, nous avons en particulier identifié un algorithme d'écriture « quasi-séquentiel » efficace pour accéder à la mémoire, ainsi que des mécanismes de bufferisation et de mise à jour d'index optimisés pour les charges typiques de l'historisation. Les résultats expérimentaux montrent un gain significatif pour les insertions par rapport à des solutions équivalentes, d'un facteur 20 à 54. Chronos est donc une solution compétitive lorsque les insertions correspondent à une proportion importante de la charge soumise au SGBD. En particulier pour les charges typiques des IGCBox, Chronos se distingue en proposant des performances globales améliorées d'un facteur 4 à 18 par rapport aux autres solutions. / Archiving industrial data is a complex issue: a large volume of data has to be stored for several decades while meeting performance requirements for real-time insertions, along with retrieval and analysis queries. For these applications, niche products have specialized in this market segment: data historians. Data historians are proprietary solutions, with license fees of tens of thousands of dollars, and whose internal mechanisms are not documented. Therefore, we first emphasized data historian specificities, with regards to functionalities as much as performance. However, archiving industrial data can occur in very different contexts. IGCBoxes for example are industrial mini PCs using MySQL for short-term data archiving in hydroelectric power stations at EDF. These equipments expose distinctive features, mainly on their storage system based exclusively on flash memory, for its reliability in an industrial environment and its low energy consumption. For historical reasons, DBMS include many hard disk drive-oriented optimizations, and the lack of adjustment for flash memories can significantly decrease performance. This type of memory thus had notable consequences on insert performance, with a substantial drop compared with hard disk drives. We therefore designed Chronos, a DBMS for historization data management on flash memories. For that purpose, we especially identified an efficient “quasi-sequential” write pattern on flash memories, along with buffer and index management techniques optimized for historization typical workloads. Experimental results demonstrate improved performance for insertions over different solutions, by a factor of 20 to 54. Chronos is therefore competitive when insertions make up an extensive part of the workload. For instance, Chronos stands out with the typical workload of IGCBoxes, with global performance improved by a factor of 4 to 18 compared with other solutions.

During the design and verification of the Hyperstone S5 flash memory controller, we developed a highly effective way to use the SystemVerilog direct programming interface (DPI) to integrate an instruction set simulator (ISS) and a software debugger in logic simulation. The processor simulation was performed by the ISS, while all other hardware components were simulated in the logic simulator. The ISS integration allowed us to filter many of the bus accesses out of the logic simulation, accelerating runtime drastically. The software debugger integration freed both hardware and software engineers to work in their chosen development environments. Other benefits of this approach include testing and integrating code earlier in the design cycle and more easily reproducing, in simulation, problems found in FPGA prototypes.

Les mémoires flash sont intégrées dans presque tous les aspects de la vie moderne car leurs uns et zéros représentent les données stockées sur les cartes à puce et dans les capteurs qui nous entourent. Dans les mémoires flash à grille flottante ces données sont représentées par la quantité de charge stockée sur une grille en poly-Si, isolée par un oxyde tunnel et un diélectrique entre grilles (IGD). Au fur et à mesure que les chercheurs et les ingénieurs de l'industrie microélectronique poussent continuellement les limites de mise à l'échelle, la capacité des dispositifs à contenir leurs informations risque de devenir compromise. Même la perte d'un électron par jour est trop élevée et entraînerait l'absence de conservation des données pendant dix ans. Étant trop faibles, les courants de fuite sont impossible à mesurer directement. Cette thèse présente une nouvelle méthode, la séparation du stress aux oxydes (OSS), pour mesurer ces courants en suivant les changements de la tension de seuil de la cellule flash. La nouveauté de la technique est que les conditions de polarisation sont sélectionnées afin que le stress se produise entièrement dans l'IGD, permettant la reconstruction d'une courbe IV de l'IGD à des tensions faibles. Cette thèse décrit également les changements de processus nécessaires pour intégrer la première mémoire flash embarquée de 40 nm basée sur un IGD d'alumine, en remplacement du SiO2/ Si3N4/SiO2 standard. L'intérêt pour les matériaux high-k vient de la motivation de créer un IGD qui est électriquement mince pour augmenter le couplage tout en étant physiquement épais pour bloquer le transport de charge. Comme la flash intégrée au noeud de 40 nm se rapproche de la production, l'approche à prendre dans les nœuds futurs doit également être discutée. Cela fournit la motivation pour le chapitre final de la thèse qui traite de la co-intégration des différents IGD avec des dispositifs logiques ayant les gilles « high-k metal » nécessaires à 28 nm et au-delà. / Flash memory circuits are embedded in almost every aspect of modern life as their ones and zeros represent the data that is stored on smart cards and in the sensors around us. In floating gate flash memories this data is represented by the amount of charge stored on a poly-Si gate, isolated by a tunneling oxide and an Inter Gate Dielectric (IGD). As the microelectronics industry’s researchers and engineering continuously push the scaling limits, the ability of the devices to hold their information may become compromised. Even the loss of one electron per day is too much and would result in the failure to retain the data for ten years. At such low current densities, the direct measurement of the leakage current is impossible. This thesis presents a new way, Oxide Stress Separation, to measure these currents by following the changes in the threshold voltage of the flash cell. The novelty of the technique is that the biasing conditions are selected such that the stress occurs entirely in the IGD, allowing for the reconstruction of an IV curve of the IGD at low biases. This thesis also describes the process changes necessary to integrate the world’s first 40 nm embedded flash based on an alumina IGD, in replacement of the standard SiO2/Si3N4/SiO2. The interest in high-k materials comes from the motivation to make an IGD that is electrically thin to increase coupling while being physically thick to block charge transport. As embedded flash at the 40 nm node nears production, the approach to be taken in future nodes must also be discussed. This provides the motivation for the final chapter of the thesis which discusses the co-integration of the different IGDs with logic devices having the high-k metal gates necessary at 28 nm and beyond.

Maitriser et optimiser les performances et la consommation énergétique dans les systèmes embarqués est aujourd'hui crucial. Pour ce faire, des techniques d'estimation de ces métriques sont utilisées dans des environnements où la réalisation de mesures est difficile. Ce travail cible l'évaluation des performances et de la consommation énergétique du service du stockage secondaire dans un système d'exploitation embarqué utilisant une mémoire flash NAND. L'un des moyens de gérer ce type de média est l'utilisation de systèmes de fichiers dédiés (Flash File Systems, FFS), pour lequel on peut constater un manque de travaux dans la littérature concernant les techniques d'estimation des performances et de la consommation. Les contributions apportées dans cette thèse s'articulent autour d'une méthodologie de modélisation pour l'estimation des performances et de la consommation des systèmes de stockage embarqués de type FFS. Cette méthodologie est divisée en trois phases. En phase d'exploration on identifie, via des micro-benchmarks, les éléments du système de stockage impactant les performances et la consommation du système embarqué. En phase de modélisation, cet impact est représenté sous la forme de modèles de différents types, dont les principaux sont les modèles fonctionnels, de performances et de consommation. Les paramètres de ces modèles sont extraits via des mesures. En phase de simulation, les modèles sont implémenté dans un simulateur, développé dans le cadre de cette thèse, permettant d'obtenir des estimations concernant les performances et la consommation d'un système de stockage à base de mémoire flash soumis à une charge d'entrées / sorties donnée. / Controlling and optimizing embedded system performance and power consumption is critical. In this context, estimation techniques are used when performing measurement campaigns is difficult due to time or financial constraints. This work targets the performance and power consumption evaluation of the secondary storage service in an embedded operating system using NAND flash memory. One way to manage flash memory is to used dedicated Flash File Systems (FFS). One can observe a lack of work in the literature concerning FFS performance and power consumption estimation techniques.The contributions presented in this thesis rely on a three steps performance and power consumption modeling methodology. During the exploration phase, we identify through micro-benchmarking the main elements of a FFS based system impacting performance and power consumption of the embedded system. In the modeling phase, this impact is represented by building models of various types. The main models types are the functional, performance and power consumption models. Models parameters are extracted through measurements on a real platform. During the simulation phase the models are implemented in a simulator. This tool allows obtaining performance and power consumption estimations concerning a flash-based storage system processing a given I/O workload.

This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part discusses actual state in using the standards for programming and testing electronic devices, with special emphasis on JTAG implementation. Next part deals with programming ARM and FPGA devices through JTAG. The programming of this devices using available software is described in the practical part of this document. Final product of this work is the programmer itself. The programmer consists of the hardware and supplement software. At the end of this thesis there is a conclusion about possible improvements and development in the future.

The rapid development of technology in the health-care sector has led to the discovery of many new illnesses and improved treatments that were not possible earlier. However, many treatments and medicines for a specific disease often come with several side effects. The accuracy in treatments with an optimal result on specified targets is therefore desired with minimum side effects. This requires that the production and the usage processes should be precise. The scope of this study is not about the medicine production phase but rather on managing a medicine schedule. How many times a medicine should be taken in a day is strongly related to its dosage and following a precise timing plays a crucial role in the individual’s health. As a solution, a pill box based on a low power display (Electronic Paper Display, EPD) together with an embedded system has been introduced by the project owner (Victrix AB, Stockholm) .The pill box should have some different functions like alarms, data logging and wireless reporting. Different types of alarms including ringtone, vibration and voice recording/playing are required as well. To be able to trace the already planned timing for taking medicines, system will be able to save and report history of the past 100 days. Since every single idea for solving different parts of the problem should be tested in real system, a Quantitative Research based on experiments be used and the best possible solution be selected and implemented in the project. Studying technical material and also related works besides analyzing generated data after each experiment were a useful tool for the system integration in this work. As the result, a pill box based on an embedded system was designed and integrated successfully. A hardware platform, in form of a prototype system based on an ARM microcontroller and a compatible embedded software have been designed, improved and tested successfully and are available. At the end of this work, the low power E-paper display works properly, alarms can be set and activated, data can be saved and also sent wirelessly. Basically, the result of this project shows how an embedded system can be specialized and programmed to be able to interact with patients and e.g. nurses in order to make a stable and continuous connection between them. Most of determined goals have been achieved and some of them be changed and modified during the work. Also a few additional functions and improvements be suggested as future work.

Le marché des objets connectés sécurisés est en plein essor et nécessite des plateformes de développement faible consommation pour des applications sans contact dans des facteurs de forme réduits. La réduction du facteur de forme impacte l’antenne et entraîne une baisse de l’énergie disponible dans la puce, qui, pour travailler à performances égales, doit voir sa consommation diminuer drastiquement. Un des principaux contributeurs à la consommation est la mémoire non-volatile embarquée (eNVM) utilisée pour le stockage et l’exécution du code. Il faut donc, pour une technologie donnée, être capable de concevoir des blocs périphériques du plan mémoire de manière à réduire la consommation au maximum. L’objectif de la thèse est donc de sélectionner une technologie eNVM très faible consommation compatible avec le procédé technologie CMOS classique, d’identifier les blocs critiques lors des opérations de la mémoire, et enfin de proposer des solutions de minimisation de la consommation pour chaque bloc critique. Pour ce faire, une étude de toutes les mémoires non volatiles embarquées disponibles sur le marché est réalisée. Il en ressort que la technologie Flash, en particulier la Flash NOR embarquée de type SuperFlash® ESF3, est la mieux adaptée pour les systèmes télé-alimentés. L’étude de la macro Flash NOR montre que durant l’écriture et l’effacement, la consommation du système est en partie liée à la génération de la haute tension par les pompes de charge. Par contre, durant la lecture, les performances globales du système sont déterminées par l’amplificateur de lecture. Ainsi, un travail de conception de chaque bloc individuel est mis en oeuvre pour réduire la consommation. / The market of secure connected devices is booming and requires low power development platforms for contactless applications in reduced form factors. The reduction in the form factor impacts the antenna size and thus leads to a decrease of the energy available in the chip, which should reduce drastically its consumption while keeping performances. One of the main contributors to the chip consumption is the embedded non-volatile memory (eNVM) used for storage and code execution. Therefore, for a given technology, it is necessary to design peripheral blocks of the memory array under strong consumption constraints. The aim of the thesis is to select a very low-power embedded nonvolatile memory technology compatible with the classical CMOS process, to identify the critical blocks during the operations of the memory, and finally to propose solutions to minimize the power consumption of each critical block.In order to do this, a study of all the embedded non-volatile memories available on the market is carried out. It emerges that the Flash technology, in particular the SuperFlash® ESF3 based NOR Flash technology, is best suited for remote-powered systems. The study of the NOR Flash macrocell shows that during write and erase operations, the system consumption is mainly related to the high voltage generation by charge pumps. However, during a read operation, overall performances of the system is determined by the sense amplifier. A design work for each individual block is then implemented to reduce consumption.

Spatial database systems widely employ spatial indexing structures to speed up the processing of spatial queries. Many of the proposed spatial indices in the literature, such as the R-tree, assume magnetic disks (i.e., HDDs) as the underlying storage device. They are termed as disk-based spatial indices. On the other hand, several spatial database applications are increasingly using flash-based Solid State Drives (SSDs) and thus, designing spatial indices for these storage devices has gained increasing attention. This is due the fact that, compared to HDDs, SSDs offer smaller size, lighter weight, lower power consumption, better shock resistance, and faster reads and writes. Hence, specific indices for SSDs, termed flash-aware spatial indices, have been proposed in the literature to deal with the intrinsic characteristics of SSDs, such as the asymmetric costs of reads and writes. However, the research to date has not been able to establish a flash-aware spatial index that actually exploits all the benefits of SSDs. This PhD thesis advances on the literature as follows. We firstly define a methodology to create spatial datasets for experimental evaluations. We also propose FESTIval, a versatile framework that provides a common and unique environment to execute experimental evaluations. Such contributions served as a foundation to conduct performance analysis along this PhD work. By using this foundation, we analyze the performance behavior of spatial indices on different storage devices, such as HDDs and SSDs. Further, we discuss the applicability of employing flash simulators on the evaluation of spatial indices. The findings of these experiments contributed to the proposal of eFIND, a generic and efficient framework for flash-aware spatial indexing. eFIND is generic because it can port a wide range of disk-based spatial indices to SSDs. eFIND is also efficient because it is based on a set of design goals that exploits SSD performance. Performance tests showed that, compared to the state of the art, eFIND improved the construction of ported disk-based spatial indices and the execution of spatial queries. For porting the R-tree (i.e., the eFIND R-tree), eFIND showed performance reductions from 43% to 77% to build spatial indices, and from 4% to 23% to execute spatial queries. For porting the xBR+-tree (i.e., the eFIND xBR+-tree), eFIND showed reductions from 28% to 83% to build spatial indices and up to 35% in the spatial query processing. / Sistemas de banco de dados espaciais empregam estruturas de indexação espaciais para acelerar o processamento de consultas espaciais. Muitos dos índices espaciais propostos na literatura, como a R-tree, assumem que os dispositivos de armazenamentos são os discos magnéticos (i.e., HDDs) e são denominados índices espaciais baseados em disco. Por outro lado, várias aplicações de banco de dados espaciais estão cada vez mais usando Solid State Drives (SSDs) baseados em memória flash e, assim, projetar índices espaciais para esses dispositivos tem ganhado cada vez mais atenção. Isso se deve ao fato de que, em comparação com os HDDs, os SSDs oferecem menor tamanho, menor peso, menor consumo de energia, melhor resistência a choques além de leituras e escritas mais rápidas. Assim, índices espaciais para memória flash têm sido propostos na literatura para lidar com as características intrínsecas dos SSDs, como os custos assimétricos de leituras e escritas. No entanto, a pesquisa até o momento não conseguiu estabelecer um índice espacial que realmente explora todos os benefícios dos SSDs. Esta tese de doutorado avança na literatura da seguinte forma. Primeiramente, é definida uma metodologia para criar conjuntos de dados espaciais para avaliações experimentais. Também é proposto FESTIval, um arcabouço versátil que fornece um ambiente comum e único para executar avaliações experimentais. Tais contribuições serviram como base para conduzir análises de desempenho ao longo deste trabalho de doutorado. Usando essa base, o comportamento de desempenho de índices espaciais em diferentes dispositivos de armazenamento, como HDDs e SSDs, é analisado. Além disso, discutese a aplicabilidade de simuladores flash na avaliação experimental de índices espaciais. Os resultados desses experimentos contribuíram para a proposta de eFIND, uma estrutura genérica e eficiente para indexação espacial em memórias flash. eFIND é genérico porque pode portar uma ampla gama de índices espaciais baseados em disco para SSDs. eFIND também é eficiente porque é baseado em um conjunto de objetivos de projeto que exploram o desempenho do SSD. Os testes de desempenho mostraram que, em comparação com o estado da arte, eFIND melhorou a construção de índices espaciais portados e a execução de consultas espaciais. Para portar a R-tree (ou seja, a eFIND R-tree), eFIND mostrou melhorias de desempenho de 43% a 77% para construir índices espaciais e de 4% a 23% para executar consultas espaciais. Para portar a xBR+-tree (ou seja, a eFIND xBR+-tree), eFIND mostrou melhorias de 28% a 83% para construir índices espaciais e de até 35% no processamento de consultas espaciais.

In Silizium-Nanokristall-Speichern werden im Gate-Oxid eines Feldeffekttransistors eingebettete Silizium Nanokristalle genutzt, um Elektronen lokal zu speichern. Die gespeicherte Ladung bestimmt dann den Zustand der Speicherzelle. Ein wichtiger Aspekt in der Technologie dieser Speicher ist die Erzeugung der Nanokristalle mit einerwohldefinierten Größenverteilung und einem bestimmten Konzentrationsprofil im Gate-Oxid. In der vorliegenden Arbeit wurde dazu ein sehr flexibler Ansatz untersucht: die thermische Ausheilung von SiO2/SiOx (x < 2) Stapelschichten. Es wurde ein Sputterverfahren entwickelt, das die Abscheidung von SiO2 und SiOx Schichten beliebiger Zusammensetzung erlaubt. Die Bildung der Nanokristalle wurde in Abhängigkeit vom Ausheilregime und der SiOx Zusammensetzung charakterisiert, wobei unter anderem Methoden wie Photolumineszenz, Infrarot-Absorption, spektroskopische Ellipsometrie und Elektronenmikroskopie eingesetzt wurden. Anhand von MOS-Kondensatoren wurden die elektrischen Eigenschaften derart hergestellter Speicherzellen untersucht. Die Funktionalität der durch Sputterverfahren hergestellten Nanokristall-Speicher wurde erfolgreich nachgewiesen. / In silicon nanocrystal memories, electronic charge is discretely stored in isolated silicon nanocrystals embedded in the gate oxide of a field effect transistor. The stored charge determines the state of the memory cell. One important aspect in the technology of silicon nanocrystal memories is the formation of nanocrystals near the SiO2-Si interface, since both, the size distribution and the depth profile of the area density of nanocrystals must be controlled. This work has focussed on the formation of gate oxide stacks with embedded nanocrystals using a very flexible approach: the thermal annealing of SiO2/SiOx (x < 2) stacks. A sputter deposition method allowing to deposit SiO2 and SiOx films of arbitrary composition has been developed and optimized. The formation of Si NC during thermal annealing of SiOX has been investigated experimentally as a function of SiOx composition and annealing regime using techniques such as photoluminescence, infrared absorption, spectral ellipsometry, and electron microscopy. To proof the concept, silicon nanocrystal memory capacitors have been prepared and characterized. The functionality of silicon nanocrystal memory devices based on sputtered gate oxide stacks has been successfully demonstrated.

New PCI-e flash cards and SSDs supporting over 100,000 IOPs are now available, with several usecases in the design of a high performance storage system. By using an array of flash chips, arranged in multiple banks, large capacities are achieved. Such multi-banked architecture allow parallel read, write and erase operations. In a raw PCI-e flash card, such parallelism is directly available to the software layer. In addition, the devices have restrictions such as, pages within a block can only be written sequentially. The devices also have larger minimum write sizes (>4KB). Current flash translation layers (FTLs) in Linux are not well suited for such devices due to the high device speeds, architectural restrictions as well as other factors such as high lock contention. We present a FTL for Linux that takes into account the hardware restrictions, that also exploits the parallelism to achieve high speeds. We also consider leveraging the parallelism for garbage collection by scheduling the garbage collection activities on idle banks. We propose and evaluate an adaptive method to vary the amount of garbage collection according to the current I/O load on the device. For large scale distributed storage systems, flash memories are an excellent choice because flash memories consume less power, take lesser floor space for a target throughput and provide faster access to data. In a traditional distributed filesystem, even distribution is required to ensure load-balancing, balanced space utilisation and failure tolerance. In the presence of flash memories, in addition, we should also ensure that the numbers of writes to these different flash storage nodes are evenly distributed, to ensure even wear of flash storage nodes, so that unpredictable failures of storage nodes are avoided. This requires that we distribute updates and do garbage collection, across the flash storage nodes. We have motivated the distributed wearlevelling problem considering the replica placement algorithm for HDFS. Viewing the wearlevelling across flash storage nodes as a distributed co-ordination problem, we present an alternate design, to reduce the message communication cost across participating nodes. We demonstrate the effectiveness of our design through simulation.