<p>The purpose of this master thesis work is to design a device that measures the loudness of sound for different frequencies. This device is divided in three parts; a microphone that captures the sound, one A/D converter that samples the sound and one FPGA which analyse the data using an FFT algorithm.</p><p>LEDs connected to the FPGA are used to indicate different output levels. A db(A) filter is applied that weights each frequency, before the different outputlevels are measured for each frequency. </p><p>This system is supposed to be a subsystem to a larger system that is developed in a company. However, because of the risk that competitors might be able to guess the next product move of the company, the company is anonymous in this report. All the components used are paid for by the company and in return the company gets an idea of the complexity of the system and a basis for future design decisions.</p>

The accurate simulation of wireless channels is important since it permits the realistic and repeatable performance measurement of wireless systems. While software simulation is a flexible method for testing hardware models, its long-running simulation time can be prohibitive in many scenarios. Prior to the availability of accurate and standardized channel models, wireless products needed to be verified using extensive and expensive field testing. A far less costly approach is to model the behavior of radio channels on a hardware simulator. Different channel characteristics should be considered to ensure the faithful simulation of wireless propagation. Among the most important characteristics are the path-loss behavior, Doppler frequency, delay distribution, fading distribution, and time, frequency, and space correlation between fading samples across different antennas. Various fading channel models have been proposed for propagation modeling in different scenarios. A good homogeneous field programmable gate array (FPGA) fading simulator needs to accurately reproduce the propagation effects, yet it also needs to be compact and fast to be effectively used for rapid hardware prototyping and simulation. In this thesis, new channel models are proposed for the compact FPGA implementation of fading channel simulators with accurate statistics. Compact hardware implementations for physical and analytical fading channel models are proposed that can simulate fading channels with more than one thousand paths on a single FPGA. We also propose design techniques for accurate and compact statistical fading channel simulation of isotropic and non-isotropic scattering in Rayleigh, Rician, Nakagami-m, and Weibull fading channels. Compact FPGA implementations are presented for multiple-antenna fading simulators for geometric one-ring models, two-ring models, elliptical models, and analytical models including the i.i.d. model, and Kronecker, Weichselberger, and VCR channel models. Finally, a fading simulation and bit error performance evaluation platform is proposed for the rapid baseband prototyping and verification of single- and multiple-antenna wireless systems.

To allow faster and more reliable wireless communication a technique is to use multiple antennas in the transmitter and receiver. This technique is called MIMO. The usage of MIMO adds complexity to the receiver that must determine what the transmitter actually sent. This thesis focuses on hardware implementation suitable for an FPGA of a detection algorithm called SUMIS. A background to detection and SUMIS in particular is given as a theoretical aid for a better understanding of how an algorithm like this can be implemented. An introduction to hardware and digital design is also presented. A subset of the operations in the SUMIS algorithm such as matrix inversion and sum of logarithmic values are analyzed and suitable hardware architectures are presented. These operations are implemented in RTL hardware using VHDL targeted for an FPGA, Virtex-6 from Xilinx. The accuracy of the implemented operations is investigated showing promising results alongside of a presentation of the necessary resource usage. Finally other approaches to hardware implementation of detection algorithms are discussed and more suitable approaches for a future implementation of SUMIS are commented on. The key aspects are flexibility through software reprogrammability and area efficiency by designing a custom processor architecture.

This thesis presents FAx86, a hardware/software full-system emulator of commodity computer systems using x86 processors. FAx86 is based upon the open-source IA-32 full-system simulator Bochs and is implemented over a single Virtex-5 FPGA. Our first prototype uses an embedded PowerPC to run the software portion of Bochs and off-loads the instruction decoding function to a low-cost hardware decoder since instruction decode was measured to be the most time consuming part of the software-only emulation. Instruction decoding for x86 architectures is non-trivial due to their variable length and instruction encoding format. The decoder requires only 3% of the total LUTs and 5% of the BRAMs of the FPGA's resources making the design feasible to replicate for many-core emulator implementations. FAx86 prototype boots Linux Debian version 2.6 and runs SPEC CPU 2006 benchmarks. FAx86 improves simulation performance over the default Bochs by 5 to 9\% depending on the workload.

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.

This thesis presents FAx86, a hardware/software full-system emulator of commodity computer systems using x86 processors. FAx86 is based upon the open-source IA-32 full-system simulator Bochs and is implemented over a single Virtex-5 FPGA. Our first prototype uses an embedded PowerPC to run the software portion of Bochs and off-loads the instruction decoding function to a low-cost hardware decoder since instruction decode was measured to be the most time consuming part of the software-only emulation. Instruction decoding for x86 architectures is non-trivial due to their variable length and instruction encoding format. The decoder requires only 3% of the total LUTs and 5% of the BRAMs of the FPGA's resources making the design feasible to replicate for many-core emulator implementations. FAx86 prototype boots Linux Debian version 2.6 and runs SPEC CPU 2006 benchmarks. FAx86 improves simulation performance over the default Bochs by 5 to 9\% depending on the workload.

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.

Today’s increased regulatory demands on emissions and hard competition drives manufacturers of heavy vehicles to try new technologies in an attempt to fulfill regulations and get ahead of competitors. This paper describes the development of a platform that is to be used as a tool to evaluate the possibilities of incorporating an FPGA in the future ECUs of Scania CV AB. Requirements for such a platform are examined and presented. These requirements are then implemented as a technology demonstrator able to sample signals from sensors and performing computations using the sampled data. The technology demonstrator is also equipped with an interface to which current ECUs can be connected.

Lossless data compression algorithms are widely used by data communication systems and data storage systems to reduce the amount of data transferred and stored. GNU Zip (GZIP) [1] is a popular compression utility that delivers reasonable compression ratios without the need for exploiting patented compression algorithms [2, 3]. The compression algorithm in GZIP uses a variation of LZ77 encoding, static Huffman encoding and dynamic Huffman encoding. Given the fact that web traffic accounts for 42% [4] of all internet traffic, the acceleration of algorithms like GZIP could be quite beneficial towards reducing internet traffic. A hardware implementation of the GZIP algorithm could be used to allow CPUs to perform other tasks, thus boosting system performance. This thesis presents a hardware implementation of GZIP encoder written in VHDL. Unlike previous attempts to design hardware-based encoders [5, 6], the design is compliant with GZIP specification and includes all three of the GZIP compression modes. Files compressed in hardware can be decompressed with the software version of GZIP. The flexibility of the design allows for hardware-based implementations using either FPGAs or ASICs. The design has been prototyped on an Altera DE2 Educational Board. Data is read and stored using an on board SD Card reader implemented in NIOS II processor. The design utilizes 20 610 LEs, 68 913 memory bits, and the on board SRAM, and the SDRAM to implement a fully functional GZIP encoder.

The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a first order passive loop-filter and (2) a - converter with a second order active loop-filter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).