De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit. / This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit.

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed. / Tjänstens säkerhet, konfidentiella uppgifter och immateriell egendom hotas av fysiska attacker, som vanligtvis inkluderar läsning och manipulering av uppgifterna. I många fall kan angripare ha tillgång till de verktyg och utrustning som kan användas för att läsa minnet eller skada det , antingen med invasiva eller icke-invasiva medel. De hemliga nycklarna som används av kryptografiska algoritmer lagras vanligtvis i ett minne. Fysiska okonabla funktioner (PUF: er) lovar att hantera sådana sårbarheter eftersom, för PUF: er, nycklarna genereras endast när det behövs och inte behöver lagras på ett avstängd chip. PUF: er använder de inneboende variationerna i tillverkningsprocessen för att generera chip-unika utgångssekvenser (svar) på en fråga (utmaning). Dessa variationer är slumpmässiga, enhetsunika, svårt att kopiera till och med av samma tillverkare med identisk process, utrustning och inställningar, och antas vara statisk, vilket gör PUF till en idealisk kandidat för generering av kryptografiska nycklar. Detta avhandlingsarbete fokuserar på en fördröjningsbaserad PUF som kallas arbiter PUF. Den använder de inneboende utbredningsfördröjningsskillnaderna för två symmetriska vägar. I detta arbete har en arbiter PUF implementerad i Altera FPGA utvärderats. Implementeringen inkluderar Verilog HDLkodning, placering och routing och kommunikationsmetoderna mellan PC och FPGA för att effektivisera testningen. De experimentella resultaten analyserades baserat på tre kriterier, tillförlitlighet, unikhet och enhetlighet. Experimentella resultat visar att arbiter PUF är tillförlitlig med avseende på temperaturvariationer, även om bitfelfrekvensen ökar när temperaturdifferensen blir större. Resultaten avslöjar också att unikheten hos PUF: erna på varje FPGA-enhet är särskilt låg men å andra sidan är proportionerna av olika svarbitar enhetliga efter att symmetrisk dirigering har utförts.

Companies developing integrated circuits are expected to enhance their products’ performance at every new release, while reducing size and power consumption. The demand for more elaborate and diverse functionality, together with a reduced time-to-market, irremediably raises costs and increases the probability of bugs. Even high-performance ASICs are not immune: the complexity of the design flow implies significant non-recurring engineering and production costs. Similar challenges affect the FPGA design flow, where the allocation of programmable logic requires considerable engineering effort. Moreover, due to the limited visibility of internal operations, isolating and back-tracing malfunctions are open challenges. Ericsson AB is exploring novel approaches to deal with this complex ecosystem.This thesis investigates the feasibility and the benefits of a flexible design approach, by developing and characterizing a Proof-of-Concept (PoC) transceiver handler for highspeed link applications. The flexibility lies in the software-based controller, exploited to handle the reset and dynamic reconfiguration of a transceiver physical layer (PHY). The objective of the software implementation is to simplify error detection and on-the-fly modification compared to a traditional HW-based controller. The firmware, running on a Nios II soft-core processor, drives the control signals while monitoring the transceiver’s status. Unexpected synchronization losses are handled by a dedicated Interrupt Service Routine.The correct HW/SW interaction has been tested through simulation, whereas the software profiling proves that the timing requirements are met (only 167µs are spent on the reset sequence). Finally, the PoC has been benchmarked against an analogous system with a traditional HW-based controller, to evaluate the drawbacks of the introduction of a soft-core processor (in terms of logic utilization and power consumption).Despite the promising engineering effort reduction, further research is required to scale up the system and move from the PoC stage towards product release. / Företag som utvecklar integrerade kretsar förväntas öka prestandan i nya produkter, och samtidigt reducera storlek samt effektförbrukning. Efterfrågan på mer komplicerad funktionalitet, tillsammans med förkortad time-to-market, orsakar oundvikligen högre kostnader och ökad sannolikhet för buggar. Även högprestererande ASICs drabbas av detta: det komplicerade designflödet resulterar i signifikanta engångskostnader för teknisk utveckling samt tillverkning. Liknande utmaningar påverkar designflödet hos FPGA:er, där allokeringen av programmerbar logik kräver påtagligt utvecklingsarbete. Eftersom insynen i interna operationer är begränsad är isolation och spårning av fel aktuella utmaningar. Ericsson AB utforskar nya tillvägagångssätt för att hantera sådana komplexa ekosystem.Det här examensarbetet undersöker genomförbarheten och fördelarna med ett flexibelt tillvägagångssätt för design, genom utveckling och karaktärisering av ett konceptbevis för en transceiver-hanterare för höghastighetslänkar. Flexibiliteten realiseras med en mjukvarubaserad kontroller som används för att hantera återställningssignaler och dynamisk rekonfigurering av en transceiver (PHY). Målet med mjukvaruimplementationen är att förenkla feldetektion samt modifikation i realtid, jämfört med en traditionell hårdvarubaserad kontroller. Mjukvaran, som körs på en Nios II soft-coreprocessor, driver styrsignaler och övervakar transceiverns status. Oväntade synkroniseringsförluster hanteras av en dedikerad avbrottshanteringsrutin. Simulationer har gjorts för att testa korrekt interaktion mellan hårdvara och mjukbara. Profilering av mjukvara visar att timingkraven uppfylls (återställningssekvensen tar endast 167 µs). Avslutningsvis har konceptbeviset jämförts med ett likvärdigt hårdvarubaserat system för att utvärdera nackdelarna med introduktionen av Nios II (vad gäller resursanvändningen och effektförbrukningen).Trots lovande resultat är den begränsade detaljnivån i konceptbeviset en tydlig begränsning. Vidare arbete måste göras för att skala upp systemet och generalisera det här nya tillvägagångssättet.

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead.

Free Space Optical (FSO) satellite communications is proving to be a key enabling technology for global connectivity with the ability to provide connection across Europe with only 12 ground stations. For this, Deutsches Zentrum für Luft- und Raumfahrt (DLR) is working on implementing a robust communication system for FSO on a Xilinx RFSoC Field Programmable Gate Array (FPGA)( ZU28DR). However, FSO is susceptible to deep fades and atmospheric turbulence affecting the quality of the communication system. Thus, measuring the performance of the communication system is crucial for choosing system parameters and designing new blocks to enhance the performance. In this thesis, a high speed test-bed implementation exploiting Parallel Pseudo Random Binary Sequence (PRBS) to measure the performance of the system is implemented. The test-bed is designed to mitigate channel fading problems to correctly calculate the Bit Error Rate (BER). The test-bed is designed to allow for online adjustment of the communication system to facilitate parameter optimizations. / FSO-satellitkommunikation visar sig vara en viktig teknologi för global anslutning med förmågan att tillhandahålla anslutning över Europa med endast 12 markstationer. För detta arbetar DLR med att implementera ett robust kommunikationssystem för FSO på en Xilinx RFSoC FPGA (ZU28DR). Men FSO är känsligt för djupa fades och atmosfärisk turbulens som påverkar kvaliteten på kommunikationssystemet. Därför är mätningen av systemets prestanda avgörande för att välja systemparametrar och designa nya block för att förbättra prestanda. I denna avhandling implementeras en höghastighets testbädd som utnyttjar parallel PRBS för att mäta systemets prestanda. Testbädden är designad för att motverka kanalförlustproblem för att korrekt beräkna BER. Testbädden är designad för att tillåta justering av kommunikationssystemet online för att underlätta optimering av parametrar

Lifetime and obsolescence of components for computer-based systems poses issues for continued usage and maintenance of the systems. This thesis investigates possible alternatives for lifetime extension of a train identification system used in Stockholm Metro. Research of other train identification systems available on the market were made to enable a cost comparison between lifetime extension and system replacement. Methods for extending lifetime of computer-based system, where components are obsolete, were investigated. Since most system documentation was inaccessible a reverse- engineering approach was chosen. Through usage of electrical schematics acquired and open-source hardware descriptions a hardware emulator was developed, which is directly compatible with the existing hardware. The total amount of resources used indicates it is possible to extend the systems lifetime at a low cost, as compared to the cost of system replacement. / Livslängd och åldrande av komponenter för datorbaserade system utgör problem för fortsatt användande och underhåll av systemen. Den här avhandlingen undersöker möjliga alternativ för livstidsförlängning av ett tågidentifieringssystem som används i Stockholms tunnelbana. Efterforskningar av andra tågidentifieringssystem tillgängliga på marknaden genomfördes för att möjliggöra en kostnadsjämförelse mellan livstidsförlängning och systemutbyte. Metoder för förlängning av livslängd av datorbaserade system, där komponenter är föråldrade, undersöktes. Då stora delar av systemdokumentationen inte var tillgänglig valdes baklängesutveckling som strategi. Genom användande av förvärvade elscheman och öppen-källkod hårdvarubeskrivningar kunde en hårdvaruemulator utvecklas, vilken är direkt kompatibel med befintlig hårdvara. Den totala resursanvändningen indikerar att det är möjligt att förlänga systemets livslängd till en låg kostnad, jämfört med kostnaden för ett systembyte.

The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how hardware is compiled for achieving high performance, which requires a long computation time. How to efficiently compile a design becomes the bottleneck for FPGA reconfiguration. It is promising to apply some techniques or concepts from software to facilitate FPGA reconfiguration. This dissertation explores such an idea by utilizing three types of low-level manipulation on FPGA logic and routing resources, i.e. relocating, mapping/placing, and routing. It implements an FMA technique for "fast reconfiguration". The FMA makes use of the software compilation technique of reusing pre-compiled libraries for explicitly reducing FPGA compilation time. Based the software concept of Autonomic Computing, this dissertation proposes to build an Autonomous Adaptive System (AAS) to achieve "self-reconfiguration". An AAS absorbs the computing complexity into itself and compiles the desired change on its own. For routing, an FPGA router is developed. This router is able to route the MCNC benchmark circuits on five Xilinx devices within 0.35 ~ 49.05 seconds. Creating a routing-free sandbox with this router is 1.6 times faster than with OpenPR. The FMA uses relocating to load pre-compiled modules and uses routing to stitch the modules. It is an essential component of TFlow, which achieves 8 ~ 39 times speedup as compared to the traditional ISE flow on various test cases. The core part of an AAS is a lightweight embedded version of utilities for managing the system's hardware functionality. Two major utilities are mapping/placing and routing. This dissertation builds a proof-of-concept AAS with a universal UART transmitter. The system autonomously instantiates the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver. / Ph. D.

In dieser Arbeit wird die Möglichkeit der Unterstützung des Hardwareentwurfs mit VHDL durch ein Hardwarebetriebssystem untersucht. Durch die Wiederverwendung von Betriebssystemmodulen sollen die Entwicklungszeit verkürzt, die Nachnutzbarkeit von Entwürfen verbessert und die Zuverlässigkeit erhöht werden. Um ein Betriebssystemkonzept umzusetzen, müssen spezielle Anforderungen an die Programmiersprache gestellt werden. Diese werden von VHDL nicht erfüllt. Daher wird ein Strukturcompiler vorgestellt, der unter Beibehaltung der Syntax der Sprache VHDL den zusätzlichen Anforderungen gerecht wird. Der Strukturcompiler verbindet das Anwendungsprogramm mit den Betriebssystemmodulen und erzeugt daraus ein VHDL-Programm, das mit den typischen FPGA-Entwicklungswerkzeugen simuliert oder synthetisiert werden kann. Bei der Entwicklung des Betriebssystems für konfigurierbare Hardware hat sich herausgestellt, dass sich dieses nur eingebettet in ein Gesamtkonzept für den Entwurf von heterogene Systeme sinnvoll anwenden lässt. Deshalb wird in dieser Arbeit eine Methode für die Entwicklung von heterogenen Systemen auf Basis eines Signalflussgraphen diskutiert. Angewendet wurde das Betriebssystemkonzept auf verschiedenen FPGA-Karten, sowohl käuflich erworbene als auch Eigenentwicklungen. Das für diese Karten erstellte Betriebssystem umfasst dabei Module zur Kommunikation zwischen FPGA und PC sowie zur Anbindung verschiedener externer Peripheriegeräte, wie z.B. Speicher. Es wurde ebenfalls untersucht wie Prozessoren als Bestandteil der konfigurierbaren Hardware in das Betriebssystemkonzept integriert werden können. Im Rahmen dieser Arbeit wurden auch viele Beispielanwendungen untersucht. Diese wurden einerseits zum Testen des Strukturcompilers und der Betriebssystemmodule benutzt. Andererseits fand das Betriebssystemkonzept für konfigurierbare Hardware auch Anwendung in verschiedenen Projekten. / This work investigates the possibility of describing a hardware design independent of special hardware. This is realized with the concept of an operating system. The re-use of operating system modules reduces the time of development and also increases the reliability. Additionally, the change of a development platform has no influence on the application algorithm anymore. In order to apply the concept of an operating system special constraints have to be fulfilled by the hardware description language, which is not supported by VHDL. For that reason a structure compiler has been developed. The structure compiler connects the application program with the operating system modules and produces a VHDL program, which can be used to simulate or to program the FPGA with the typical VHDL development tools. In the progress of developing the operating system concept for reconfigurable hardware it was realized that such a concept can only be used in connection with a design methodology for heterogeneous systems. In this work a design methodology based on a declarative language represented as signal flow graph is discussed. The operating system concept for reconfigurable hardware was tested on different FPGA boards. For these cards an operating system was developed. The operating system contains modules for the communication with the PC over different interfaces as well as modules for accessing different exterior peripheries, i.e. memory. Additionally, the integration of processors as part of the configurable hardware within the operating system concept was investigated. For the verification of the structure compiler and the operating system modules some examples have been developed. The operating system concept for configurable hardware was also applied in different projects.

Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.

<p>Основни допринос дисертације су дефинисани методи истовременог<br />формирања више снопова код пријемника мултистатичког радара. Тиме<br />иста пријемна антена прима сигнале из целе хемисфере уз појачања<br />адекватна величини антене. Показано је да дефинисане методе,<br />примењене на конформне антене омогућавају формирање више<br />стотина снопова са само једним FPGA колом. Приказане су и<br />могућности паралелне обраде оволиког броја примљених радарских<br />сигнала. У пријемнику су обједињене функције претраживања простора<br />и праћења циљева. Процењене су величине простора који се може<br />покрити оваквим системом уз искључиву примену комерцијалне<br />технологије. Дате су методе синхронизације предајника и пријемника<br />засноване на технологији ултраширокопојасних комуникација.<br />&nbsp;</p> / <p>Osnovni doprinos disertacije su definisani metodi istovremenog<br />formiranja više snopova kod prijemnika multistatičkog radara. Time<br />ista prijemna antena prima signale iz cele hemisfere uz pojačanja<br />adekvatna veličini antene. Pokazano je da definisane metode,<br />primenjene na konformne antene omogućavaju formiranje više<br />stotina snopova sa samo jednim FPGA kolom. Prikazane su i<br />mogućnosti paralelne obrade ovolikog broja primljenih radarskih<br />signala. U prijemniku su objedinjene funkcije pretraživanja prostora<br />i praćenja ciljeva. Procenjene su veličine prostora koji se može<br />pokriti ovakvim sistemom uz isključivu primenu komercijalne<br />tehnologije. Date su metode sinhronizacije predajnika i prijemnika<br />zasnovane na tehnologiji ultraširokopojasnih komunikacija.<br />&nbsp;</p> / <p>Main contribution of this dissertation are the new digital beam forming<br />methods, suitable for applicable in multibeam conformal antenna. These<br />methods maintain antenna gain independently of beam positions in whole<br />hemisphere, scanned by the radar. Few hundred beams could be formed by<br />the only one FPGA. Parallel digital signal processing of these beams can be<br />also performed by the only one FPGA. Functions of surveillance and tracking<br />radar are joint in the one receiver. High accuracy in time and frequency<br />synchronization between receiver and transmitter is enabled by UWB.</p>