Η παρούσα ειδική ερευνητική εργασία εκπονήθηκε στα πλαίσια του Διατμηματικού Προγράμματος Μεταπτυχιακών Σπουδών Ειδίκευσης στην “Ηλεκτρονική και Επεξεργασία της Πληροφορίας” στο Τμήμα Φυσικής του Πανεπιστημίου Πατρών. Αντικείμενο της παρούσας εργασίας είναι η σχεδίαση και ανάπτυξη ενός βασικού μικροϋπολογιστικού συστήματος με τη χρήση της VHDL και FPGAs. Το σύστημα βασίζεται σε μία επαυξημένη, σε δυνατότητες, εκδοχή της σχετικά απλής cpu του Carpinelli και ενσωματώνει τη δυνατότητα παράλληλης διασύνδεσης μίας σειράς περιφερειακών διατάξεων και υποκυκλωμάτων. Στο πρώτο κεφάλαιο παρουσιάζεται πλήρως η σχεδίαση ενός τέτοιου συστήματος και μελετάται η δομή των επιμέρους δομικών στοιχείων που το απαρτίζουν. Στο δεύτερο κεφάλαιο παρουσιάζεται η περιγραφή του μικροϋπολογιστικού συστήματος σε γλώσσα VHDL και η πλήρης εξομοίωσή του με τη βοήθεια του λογισμικού Quartus v7.2 της ALTERA. Στο τελευταίο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροϋπολογιστικού συστήματος στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA. / This project objective is the design and development of an FPGA based microcomputer system in VHDL. The system is based on an enhanced version of Carpinelli’s relative simple cpu and is implemented with parallel input and output ports and interrupts. The first chapter presents the full design of such a system and study the structure of the individual components that compose it. The second chapter presents the implementation of the microcomputer system in VHDL and the simulation results using Quartus v7.2 software suite. The last chapter presents the implementation of the system in a FPGA using DE2 development board of ALTERA.

Τα ενσωματωμένα υπολογιστικά συστήματα έχουν αρχίσει να χρησιμοποιούνται ολοένα και περισσότερο τα τελευταία χρόνια, όχι μόνο σε βιομηχανικές ή άλλες εξεζητημένες εφαρμογές αλλά και στην καθημερινότητα μας. Αυτό οφείλεται στο γεγονός ότι η συγκεκριμένη τεχνολογία είναι φτηνότερη, ευέλικτη και λιγότερο ενεργοβόρος σε σχέση με τα αντίστοιχα ηλεκτρονικά κυκλώματα που χρησιμοποιούνταν παλιότερα. Η παρούσα διπλωματική εργασία περιγράφει αναλυτικά τη διαδικασία για τη σωστή ρύθμιση του συστήματος μας και την μεταγλώττιση (compilation) του πυρήνα του Linux προκειμένου να τρέχει χωρίς προβλήματα πάνω στην FPGA πλακέτα της Xilinx, Virtex 5. Σαν επεξεργαστή επιλέξαμε να χρησιμοποιήσουμε τον soft - core επεξεργαστή της Xilinx microblaze,προσθέτοντας σαν επιπλέον περιφερειακά την οθόνη TFT καθώς και την θύρα PS/2. Στη συνέχεια προκειμένου να καταδείξουμε τις δυνατότητες που έχει το σύστημα που “χτίσαμε”, εγκαταστήσαμε γραφικό περιβάλλον με ορισμένες εφαρμογές και εκτελούμε κρυπτογραφικές συναρτήσεις από το terminal του λειτουργικού μας. / The embedded computer systems have recently started to be present in a number of implementations, not only in the industrial setting but also in normal life applications. This is due to the fact that this particular technology is cheaper, more efficient and less power - consuming than its dedicated electronic counterparts. In this diploma thesis we will study the process for the proper configuration of our system and the compilation of Linux Kernel in order to have a completely functional embedded system on the Xilinx' s FPGA board, Virtex 5. We used the Microblaze soft - core processor and we added the TFT monitor and the PS/2 port as extra components to our system. Furthermore in order to present the capabilities of our system, we added the Nano - X graphical user interface and we run cryptographic algorithms through the terminal of the operating system.

Submitted by João Arthur Martins (joao.arthur@ufpe.br) on 2015-03-11T18:49:30Z No. of bitstreams: 2 DISSERTAÇÃO Luis Carlos da Silva Júnior.pdf: 7394999 bytes, checksum: 8cd60b1a203e6c89997958d7bb900200 (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) / Approved for entry into archive by Daniella Sodre (daniella.sodre@ufpe.br) on 2015-03-13T13:11:22Z (GMT) No. of bitstreams: 2 DISSERTAÇÃO Luis Carlos da Silva Júnior.pdf: 7394999 bytes, checksum: 8cd60b1a203e6c89997958d7bb900200 (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) / Made available in DSpace on 2015-03-13T13:11:22Z (GMT). No. of bitstreams: 2 DISSERTAÇÃO Luis Carlos da Silva Júnior.pdf: 7394999 bytes, checksum: 8cd60b1a203e6c89997958d7bb900200 (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Previous issue date: 2013-09-13 / Nesta dissertação de mestrado é introduzida uma nova ferramenta de síntese de alto nível chamada SynMaker que recebe como entrada um código de alto nível Orientado a Objetos escrito em Java ou SystemVerilog e gera código RTL que pode ser sintetizado para uma placa de prototipação alvo. A geração de código RTL leva em conta características do código orientado a objetos tais como classes, abstração, encapsulamento e algumas restrições relativas a polimorfismo, herança, utilização de construtores dentre outras especificadas neste trabalho e, por fim, integra o resultado com uma plataforma FPGA que inclui uma câmera e um display para exibir os resultados. O fluxo de projeto implementado no SynMaker foi especialmente concebido para aplicações de processamento de imagem e vídeo. Uma vantagem desta abordagem é que ela abstrai completamente o fluxo da ferramenta Quartus II, o designer descreve a aplicação de processamento de imagem em uma linguagem de alto nível de orientação a objeto, utilizando uma biblioteca de componentes da plataforma e gera código para a Plataforma de Desenvolvimento Terasic DE2-70. Esta plataforma de desenvolvimento inclui uma câmera digital e display, sendo uma plataforma ideal para a prototipagem de aplicações de filtros de processamento de imagem e vídeo. Em seu estado atual o SynMaker pode executar uma síntese de alto nível de uma forma simplificada, realizando um mapeamento direto de uma AST (Abstract Syntax Tree) para código RTL. Os resultados experimentais para a síntese de filtros de processamento de imagem são apresentados e demonstram a eficácia do funcionamento da ferramenta de síntese proposta.

Orientador: Furio Damiani / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T03:48:46Z (GMT). No. of bitstreams: 1 Bernardo_Rodrigo_M.pdf: 3176872 bytes, checksum: a6a7b540ec1bfd0dbe839744ef1adf5e (MD5) Previous issue date: 2009 / Resumo: Este trabalho apresenta o desenvolvimento e a prototipagem de um nó de acesso utilizado como prova de conceito de redes de chaveamento de pacotes ópticos. Ele descreve as arquiteturas propostas para a rede e o nó de acesso, juntamente com o desenvolvimento detalhado do hardware, desde a concepção até os testes finais dos módulos (placas), e do núcleo de processamento implementado em dispositivo de lógica programável, que constitui a inteligência da rede. O nó de acesso foi concebido de forma modular, com quatro módulos desenvolvidos para compor o elemento principal da rede, cada um com tecnologia e função especifica. O trabalho também descreve os testes realizados com os protótipos, demonstrando que os requisitos inicialmente propostos foram alcançados / Abstract: This work presents the development and prototyping of an access node for an optical packet switching network. The network's architecture and the access node proposals are described, as well as the detailed hardware development, from the conception to modules' (boards) final tests and core processing implemented on PLDs, which constitutes the intelligence of the network. The access node was conceived in a modular way, with four modules developed to compose the main element of the network, each with its proper technology and function. The work also describes the tests performed on the prototypes, showing that the proposed requirements were met / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientadores: Dalton Soares Arantes, Fabbryccio Akkazzha Chaves Machado Cardoso / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T17:04:47Z (GMT). No. of bitstreams: 1 Moreira_VeruskaRodrigues_M.pdf: 1358124 bytes, checksum: b78b10c0a05e8732e9f54ceb1cbbdceb (MD5) Previous issue date: 2009 / Resumo: Esta dissertação apresenta a concepção e o desenvolvimento de uma plataforma em hardware reconfigurável denominada REDLART - REconfigurable Digital Laboratory for Advanced Research and Teaching, visando soluções de laboratório a distância aplicadas ao ensino e ao trabalho colaborativo em sistemas digitais. A plataforma é baseada em dispositivos FPGA (Field Programmable Gate Array) para desenvolvimento de circuitos digitais com aplicações em processamento digital de sinais, sistemas de comunicações digitais, sistemas de controle e áreas afins. Além da plataforma de hardware, também foi concebida e implementada uma arquitetura de sistema, composta por um conjunto de softwares cliente-servidor, com o objetivo de viabilizar o acesso remoto através da gerência e da configuração de experimentos desenvolvidos na REDLART. Tal sistema, incluindo a própria REDLART, possibilita o desenvolvimento de novos experimentos e sua disponibilização na Web, resultando em um WebLab reconfigurável para sistemas digitais. Testes foram realizados em nível de hardware e software para a validação da plataforma / Abstract: This thesis presents a reconfigurable hardware platform called REDLART (REconfigurable Digital Laboratory for Advanced Research and Teaching), designed to enable laboratory applications in distance learning and collaborative work in digital systems. The platform is based on FPGA devices (Field Programmable Gate Array) to develop digital circuit applications for digital signal processing, digital communication systems, control systems and related areas. Besides the hardware platform, a system architecture consisting of a set of client-server software was also designed and implemented in order to enable the remote access through the management and configuration of experiments developed in REDLART. By using the client-server software with the REDLART platform, new experiments can be developed and made available on the Web, resulting in a WebLab for reconfigurable digital systems. Tests were performed at the hardware and software levels for the validation of the platform / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Random number generators are basic building blocks of modern cryptographic systems. Usually pseudo random number generators, carefully constructed deter- ministic algorithms that generate seemingly random numbers, are used. These are built upon foundations of thorough mathematical analysis and have been subjected to stringent testing to make sure that they can produce pseudo random sequences at a high bit-rate with good statistical properties. A pseudo random number generator must be initiated with a starting value. Since they are deterministic, the same starting value used twice on the same pseudo random number generator will produce the same seemingly random sequence. Therefore it is of utmost importance that the starting value contains enough en- tropy so that the output cannot be predicted or reproduced in an attack. To gen- erate a high entropy starting value, a true random number generator that uses sampling of some physical non-deterministic phenomenon to generate entropy, can be used. These are generally slower than their pseudo random counterparts but in turn need not generate the same amount of random values. In field programmable gate arrays (FPGA), generating random numbers is not trivial since they are built upon digital logic. A popular technique to generate entropy within a FPGA is to sample jittery clock signals. A quite recent technique proposed to create a robust clock signals, that contains such jitter, is to use self- timed ring oscillators. These are structures in which several events can propagate freely at an evenly spaced phase distribution. In this thesis self-timed rings of six different lengths is implemented on a spe- cific FPGA hardware. The different implementations are tested with the TestU01 test suite. The results show that two of the implementations have a good oscilla- tory behaviour that is well suited for use as random number generators. Others exhibit unexpected behaviours that are not suited to be used in a random num- ber generator. Two of the implemented random generators passed all tests in the TestU01 batteries Alphabit and BlockAlphabit. One of the generators was deemed not fit for use in a random number generator after failing all of the tests. The last three were not subjected to any tests since they did not behave as ex- pected.

The goal of this project is to develop a flexible multi-core hardware test-bed on field programmable gate array (FPGA) that can be used to effectively validate the theoretical research on multi-core computing, especially for the power/thermal aware computing. Based on a commercial FPGA test platform, i.e. Xilinx Virtex5 XUPV5 LX110T, we develop a homogeneous multi-core test-bed with four software cores, each of which can dynamically adjust its performance using software. We also enhance the operating system support for this test platform with the development of hardware and software primitives that are useful in dealing with inter-process communication, synchronization, and scheduling for processes on multiple cores. An application based on matrix addition and multiplication on multi-core is implemented to validate the applicability of the test bed.

This thesis presents a generalized approach for the fully digital design and implementation of chaos generators through the numerical solution of chaotic ordinary differential equations. In particular, implementations use the Euler approximation with a fixed-point twos complement number representation system for optimal hardware and performance. In general, digital design enables significant benefits in terms of power, area, throughput, reliability, repeatability and portability over analog implementations of chaos due to lower process, voltage and temperature sensitivities and easy compatibility with other digital systems such as microprocessors, digital signal processing units, communication systems and encryption systems. Furthermore, this thesis introduces the idea of implementing multidimensional chaotic systems rather than 1-D chaotic maps to enable wider throughputs and multiplier-free architectures that provide significant performance and area benefits. This work focuses efforts on the well-understood family of autonomous 3rd order "jerk" chaotic systems. The effect of implementation precision, internal delay cycles and external delay cycles on the chaotic response are assessed. Multiplexing of parameters is implemented to enable switching between chaotic and periodic modes of operation. Enhanced chaos generators that exploit long-term divergence in two identical systems of different precision are also explored. Digital design is shown to enable real-time controllability of 1D multiscroll systems and 4th order hyperchaotic systems, essentially creating non-autonomous chaos that has thus far been difficult to implement in the analog domain. Seven different systems are mathematically assessed for chaotic properties, implemented at the register transfer level in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA. The statistical properties of the output are rigorously studied using the NIST SP. 800-22 statistical testing suite. The output is adapted for pseudo random number generation by truncating statistically defective bits. Finally, a novel post-processing technique using the Fibonacci series is proposed and implemented with a non-autonomous driven hyperchaotic system to provide pseudo random number generators with high nonlinear complexity and controllable period length that enables full utilization of all branches of the chaotic output as statistically secure pseudo random output.

abstract: With the exponential growth in video content over the period of the last few years, analysis of videos is becoming more crucial for many applications such as self-driving cars, healthcare, and traffic management. Most of these video analysis application uses deep learning algorithms such as convolution neural networks (CNN) because of their high accuracy in object detection. Thus enhancing the performance of CNN models become crucial for video analysis. CNN models are computationally-expensive operations and often require high-end graphics processing units (GPUs) for acceleration. However, for real-time applications in an energy-thermal constrained environment such as traffic management, GPUs are less preferred because of their high power consumption, limited energy efficiency. They are challenging to fit in a small place. To enable real-time video analytics in emerging large scale Internet of things (IoT) applications, the computation must happen at the network edge (near the cameras) in a distributed fashion. Thus, edge computing must be adopted. Recent studies have shown that field-programmable gate arrays (FPGAs) are highly suitable for edge computing due to their architecture adaptiveness, high computational throughput for streaming processing, and high energy efficiency. This thesis presents a generic OpenCL-defined CNN accelerator architecture optimized for FPGA-based real-time video analytics on edge. The proposed CNN OpenCL kernel adopts a highly pipelined and parallelized 1-D systolic array architecture, which explores both spatial and temporal parallelism for energy efficiency CNN acceleration on FPGAs. The large fan-in and fan-out of computational units to the memory interface are identified as the limiting factor in existing designs that causes scalability issues, and solutions are proposed to resolve the issue with compiler automation. The proposed CNN kernel is highly scalable and parameterized by three architecture parameters, namely pe_num, reuse_fac, and vec_fac, which can be adapted to achieve 100% utilization of the coarse-grained computation resources (e.g., DSP blocks) for a given FPGA. The proposed CNN kernel is generic and can be used to accelerate a wide range of CNN models without recompiling the FPGA kernel hardware. The performance of Alexnet, Resnet-50, Retinanet, and Light-weight Retinanet has been measured by the proposed CNN kernel on Intel Arria 10 GX1150 FPGA. The measurement result shows that the proposed CNN kernel, when mapped with 100% utilization of computation resources, can achieve a latency of 11ms, 84ms, 1614.9ms, and 990.34ms for Alexnet, Resnet-50, Retinanet, and Light-weight Retinanet respectively when the input feature maps and weights are represented using 32-bit floating-point data type. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019

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