Σε μία εποχή όπου η ψηφιοποίηση δεδομένων έχει αυξηθεί ραγδαία η ανάγκη για τη βέλτιστη μετάδοσή τους είναι απαραίτητη. Από τα πλέον σημαντικά μέρη των προτύπων μετάδοσης είναι η κωδικοποίηση του καναλιού μέσω ειδικών αλγορίθμων ώστε να επιτευχθεί η εύρεση και διόρθωση τυχών λαθών. Οι κώδικες Bose, Chaudhuri και Hocquenghem (BCH) είναι τέτοιου είδους κώδικες που χρησιμοποιούνται ευρέως σε εφαρμογές όπως τα CD, DVD, σκληροί δίσκοι, δίσκοι στερεάς κατάστασης (SSD) και το πρότυπο δορυφορικής μετάδοσης τηλεόρασης υψηλής ανάλυσης (HDTV), DVB-S2. Στην παρούσα διπλωματική εργασία σχεδιάστηκε και υλοποιήθηκε κωδικοποιητής και αποκωδικοποιητής BCH για τις 11 περιπτώσεις κανονικού πλαισίου που προσφέρει το πρότυπο DVB-S2. Κύριος στόχος ήταν η όσο το δυνατόν καλύτερη υλοποίηση με γνώμονα το μέγεθος, με τη χρήση κοινών κυκλωμάτων και για τις 11 περιπτώσεις. Αποτέλεσμα αυτής της βελτιστοποίησης μεγέθους, ήταν κάποιες τεχνικές βελτιστοποίησης της ταχύτητας αποκωδικοποίησης, όπως το shortening, να μη χρησιμοποιηθούν καθώς θα είχαν ως αποτέλεσμα την αύξηση της επιφάνειας μερών του αποκωδικοποιητή κατά περίπου 11 φορές. Καθώς σκοπός της διπλωματικής ήταν η μελέτη της απόδοσης των κωδίκων BCH, μελετήθηκε ο ρυθμός λαθών σε διάφορες τιμές της αναλογίας ενέργειας – θορύβου (Eb / N0 ), αφού πρώτα υλοποιήθηκε σε FPGA. / The amount of digital information is growing rapidly the recent decades, making transmission optimization one of the top priorities in digital information systems. One of the main parts of every transmission standard is channel encoding, with the use of algorithms aimed at finding and correcting errors (Forward Error Correction – FEC). Such codes are Bose, Chaudhuri and Hocquenghem (BCH) code, which are widely used in applications like CDs, DVDs, Hard Drives, Solid State Drives (SSDs) and DVB-S2, a satellite transmission standard mostly used for High Definition Television (HDTV). This thesis sets out to account for the design and implementation of a BCH encoder and decoder for all 11 different code rates proposed by the DVB-S2 standard for normal frames. The design was area optimized in order for all 11 code rate encoders and decoders to work on the same FPGA. This lead to some optimization techniques being unused. Even though the codes are shortened, no shortening algorithms which aim at clock cycle optimization were used. Were they used, would lead parts of the decoder to be almost 11 times larger. The main goal of the thesis is to analyze the performance of the codes, so the error rate was measured under different values of the energy to noise ratio (Eb/ N0 ).

Distributed generation that utilizes 5-10kW Solid Oxide Fuel Cells requires power electronics to optimize the overall system efficiency while reducing the cost. The Adaptive Energy Zero-Voltage-Switching Phase-Shift-Modulated Full-Bridge (AE-ZVS-PSM-FB) topology meets these criteria under all loading conditions, but suffers from complexity associated with an analog control implementation. This thesis presents a novel Look-Up-Table (LUT) based digital controller required for such converter. The applied design approach also reduces the design time and controller requirements, which in turn decreases the overall system cost. Steady-state analysis for the AE-ZVS-PSM-FB converter is performed using a piece-wise equivalent circuit model. This analysis is used to verify the LUT concept that forms the basis for the proposed LUT-based digital controller. The proposed LUT-based digital control algorithm is developed and verified using Field Programmable Gate Array (FPGA) Logic platform. Design procedures and operational function under steady state and step change conditions are presented. Simulation results demonstrate the LUT concept in the AE-ZVS-PSM-FB converter, and the simplicity of the proposed LUT-based digital controller in producing the expected switching sequence. Simulation results were also produced showing successful dynamic response of LUT-based digital controller interconnected with the converter under different operating conditions. A Xilinx FPGA demonstration board was used to generate experimental switching sequence results to demonstrate the simplicity of the proposed controller. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-09-25 10:26:39.909

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of iterations. The design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit implementation of digit-online decoder in single-frame mode, the minimum throughput achieved is 740 Mb/s at low SNRs. For the case of 11-bit LLR digit-online decoder in frame-interlaced mode, the minimum throughput achieved is 1363 Mb/s. Detailed analysis such as effect of SNR and LLR precision on decoder power is presented. Also, the effect of changing LLR precision on max clock frequency and logic utilization on the parallel and the digit-online decoders is studied. Alongside, power per iteration for a 6-bit LLR input digit-online decoder is also reported.

Zugl.: Rostock, Univ., Diss., 2007

Zugl.: Braunschweig, Techn. Univ., Diss., 2008

Στόχος της παρούσας Διπλωματικής Εργασίας είναι ο σχεδιασμός και υλοποίηση ενός Κρυπτογραφικού Συστήματος με βάση τον Αλγόριθμο κατακερματισμού JH. Ο σχεδιασμός του κρυπτογραφικού αυτού συστήματος έγινε με τη χρήση γλώσσας VHDL (Very High Speed Integrated Circuits hardware description language) και στη συνέχεια η υλοποίηση αυτή έγινε πάνω σε πλατφόρμα FPGA (Field Programmable Gate Array). Ο αλγόριθμος JH είναι ένας αλγόριθμος κατακερματισμού (hash function) ο οποίος σχεδιάστηκε στα πλαίσια του διαγωνισμου κρυπτογραφιας NIST (National Institute of Standards and Technology). Η πρώτη του έκδοση έγινε στις 31 Οκτωβρίου 2008 ενώ η τελική του έκδοση έγινε στις 16 Ιανουαρίου 2011. Ο Αλγόριθμος JH έχει τρεις υποκατηγορίες. Υπάρχει ο JH-224, JH-256, JH-384 και ο JH-512. Βασικό χαρακτηριστικό του αλγορίθμου αυτού είναι το γεγονός πώς οι λειτουργίες που συμβαίνουν σε κάθε γύρο είναι ίδιες. Επίσης σημαντικό γνώρισμα ειναι η ασφάλεια που παρέχει ο αλγόριθμος αυτός καθώς ο μεγάλος αριθμός των ενεργών S-boxes που χρησιμοποιούνται και ταυτόχρονα το γεγονός ότι σε κάθε γύρο χρησιμοποιείται ένα διαφορετικό κλειδι το οποίο παράγεται εκεινη τη στιγμή και δεν ειναι αποθηκευμένο σε ένα σημείο, στο οποίο θα μπορούσε κάποιος να επέμβει, κάνει το σύστημά μας εξαιρετικά δυνατό και ανθεκτικό απέναντι σε επιθέσεις όπως είναι η διαφορική κρυπτανάλυση. Για την εξακρίβωση της ορθής λειτουργίας του συστήματος χρησιμοποιήθηκε μία υλοποίηση του Αλγορίθμου JH σε γλώσσα C. Χρησιμοποιώντας την υλοποίηση αυτή κάθε φορά που θέλουμε να κρυπτογραφήσουμε ένα μήνυμα το οποίο είναι μία σειρά από bit, λαμβάνουμε το κρυπτογραφημένο μήνυμα. Αυτο το κρυπτογραφημένο μήνυμα το συγκρίνουμε με αυτό που παίρνουμε στην έξοδο του συστήματος JH που σχεδιάσαμε και με αυτό το τρόπο επιβεβαιώνουμε την ορθότητα του αποτελέσματος. Ύστερα από την non-pipelined υλοποίηση του συστήματος αυτού, χρησιμοποιήθηκε η τεχνική της συσωλήνωσης (pipeline). Πιο συγκεκριμένα εγιναν 4 διαφορετικές pipelined υλοποιήσεις με 2,3,6 και 7 στάδια. Σκοπός είναι για κάθε μία pipelined υλοποίηση να γίνει έλεγχος σε θέματα απόδοσης, κατανάλωσης ισχύος καθώς επίσης και σε θέματα επιφάνειας. Στη συνέχεια γίνεται μία σύγκριση στα προαναφερθέντα θέματα μεταξύ των διαφορετικών pipelined υλοποιήσεων και με την non-pipelined υλοποίηση του κρυπτογραφικού συστήματος JH. Επίσης αξίζει να σημειωθεί πώς γίνεται ιδιαίτερη αναφορά στο throughput και στο throughput per area των pipelined υλοποιήσεων. Από τα πειραματικά αποτελέσματα που προέκυψαν η JH NON PIPELINED υλοποίηση έχει απόδοση 97 MHz με κατανάλωση ισχύος 137mW και συνολική επιφάνεια 2284 slices σε SPARTAN 3E FPGA συσκευή. Ενώ από την ανάλυση της JH NON PIPELINED υλοποίησης και των 4 pipelined υλοποιήσεων σε 4 διαφορετικά FPGA (2 της οικογένειας SPARTAN και 2 της οικογένειας VIRTEX) συμπεραίνουμε πώς στην οικογένεια VIRTEX η κατανάλωση ισχύος είναι πάντα μεγαλύτερη σε σχεση με την οικογένεια SPARTAN. / The purpose of this Thesis Project is the design and implementation of a Cryptographic System using the JH Hash Algorithm. The design of this Cryptographic System was performed using the VHDL language (Very High Speed Integrated Circuits hardware description language) and then this implementation was executed on a FPGA platform (Field Programmable Gate Array).The JH Algorithm is a hash algorithm that was developed during the NIST (National Institute of Standards and Technology) Cryptography Competition. Its first version was released on 31 October 2008 while its last version was released on 16 January 2011. The JH Hash Algorithm has three subcategories. There is JH-224, JH-256, JH-384, and JH-512. Basic characteristic of this Algorithm is the fact that the functions that are executed in each round are identical. Moreover important characteristic is the security that this Algorithm provides us while the big number of active S-Boxes that is used and in the same time the fact that in each round a different key is produced on the fly, and is not stored in a place that a third person could have access, makes our system really strong and resistant to attacks such as the differential attack. To confirm the right functionality of the system the implementation of the JH Algorithm in C Language is used. Using this implementation each time we want to cipher a message, which is a sequence of bits, we get the message digest. This message digest is compared with the message digest that we get from the JH system that we developed with VHDL and in this way we confirm the correctness of the result. After the non pipelined implementation of the JH system the pipeline technique was used. To be more specific 4 different pipelined implementations with 2, 3, 6 and 7 stages were performed. The target was to check the performance, area and power dissipation for each pipelined implementation. Next a comparison was performed between the various pipelined implementations and the non pipelined implementation for the above mentioned issues. In addition to this it is worth to mention that considerable reference is made for throughput and throughput per area for the pipelined implementations. According to the experimental results the JH NON PIPELINED implementation has a performance of 97 MHz, with power dissipation of 137mW and a total area of 2284 Slices on SPARTAN 3E FPGA device. From the JH NON PIPELINED implementation and the other 4 pipelined implementations on 4 different FPGA Devices (2 from the VIRTEX family and 2 from the SPARTAN family) we concluded that the power dissipation is bigger in VIRTEX family devices in comparison to SPARTAN family Devices.

Οι κρυπτογραφικές συναρτήσεις κατακερματισμού αποτελούν στις μέρες μας ένα από τα δημοφιλέστερα συστατικά των κρυπτογραφικών συστημάτων, λόγω των ιδιαίτερων ιδιοτήτων τους. Λαμβάνοντας υπόψη τη συνεχή αύξηση του όγκου δεδομένων και των ταχυτήτων επικοινωνίας, η χρήση μιας συνάρτησης κατακερματισμού με χαμηλή ρυθμοαπόδοση μπορεί να επιβραδύνει το συνολικό ψηφιακό τηλεπικοινωνιακό σύστημα. Ο σχεδιασμός ενός δεδομένου αλγορίθμου κατακερματισμού ώστε να έχει τη βέλτιστη ρυθμοαπόδοση αποτελεί ζήτημα μεγάλης σημασίας. Στη συγκεκριμένη διπλωματική εργασία παρουσιάζεται μια μεθοδολογία σχεδιασμού με στόχο τη βέλτιστη ρυθμοαπόδοση κρυπτογραφικών αλγορίθμων που βασίζονται σε συγκεκριμένη επαναληπτική μορφή. Για το σκοπό αυτό αναπτύχθηκε ένα λογισμικό, που συνδυάζει δύο τεχνικές, τον επαναχρονισμό και την ξεδίπλωση, παράγοντας το βέλτιστο σχεδιαστικό αποτέλεσμα. Η μεθοδολογία εφαρμόστηκε σε δύο δημοφιλείς συναρτήσεις κατακερματισμού, τις SHA-1 και SHA-256. Οι μετασχηματισμένοι αλγόριθμοι συνθέθηκαν και υλοποιήθηκαν σε FPGA, επιβεβαιώνοντας την αποτελεσματικότητα της μεθόδου. / Nowadays, cryptographic hash functions are one of the most popular primitive components in the cryptographic systems, due to their key features. Considering that data sizes and communication speeds are increasing every year, the use of a hash algorithm with low throughput can be a bottle neck in the digital communication system. Designing a given hash algorithm to be throughput optimum is a critical issue. In this diploma thesis a design methodology is presented which oprimizes the throughput of cryptographic hash functions that rely on a specific iterative structure. For this purpose, a software was designed combining two techniques, retiming and unfolding, that generates the optimal throughput design. The methodology was applied to two popular hash algorithms, SHA-1 and SHA-256. The transformed algorithms were synthesized and implemented in a FPGA device, confirming its effectiveness.

O paradigma Network Function Virtualization (NFV) promete tornar as redes de computadores mais escaláveis e flexíveis, através do desacoplamento das funções de rede de hardware dedicado e fornecedor específico. No entanto, funções de rede computacionalmente intensivas podem ser difíceis de virtualizar sem degradação de desempenho. Neste contexto, Field-Programmable Gate Arrays (FPGAs) têm se mostrado uma boa opção para aceleração por hardware de funções de rede virtuais que requerem alta vazão, sem se desviar do conceito de uma infraestrutura NFV que visa alta flexibilidade. A avaliação de expressões regulares é um mecanismo importante e computacionalmente intensivo, usado para realizar Deep Packet Inpection, que pode ser acelerado por FPGA para atender aos requisitos de desempenho. Esta solução, no entanto, apresenta novos desafios em relação aos requisitos de confiabilidade. Particularmente para FPGAs baseados em SRAM, soft errors na memória de configuração são uma ameaça de confiabilidade significativa. Neste trabalho, apresentamos um mecanismo de tolerância a falhas abrangente para lidar com falhas de configuração na funcionalidade de módulos de avaliação de expressões regulares baseados em FPGA. Além disso, é introduzido um mecanismo de correção de erros que considera o posicionamento desses módulos no FPGA para reduzir o tempo de reparo do sistema, melhorando a confiabilidade e a disponibilidade. Os resultados experimentais mostram que a taxa de falha geral e o tempo de reparo do sistema podem ser reduzidos em 95% e 90%, respectivamente, com custos de área e performance admissíveis. / The Network Function Virtualization (NFV) paradigm promises to make computer networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, Field-Programmable Gate Arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for SRAM-based FPGAs, soft errors on the configuration memory are a significant dependability threat. In this work we present a comprehensive fault tolerance mechanism to deal with configuration faults on the functionality of FPGA-based regular expression matching engines. Moreover, a placement-aware scrubbing mechanism is introduced to reduce the system repair time, improving the system reliability and availability. Experimental results show that the overall failure rate and the system mean time to repair can be reduced in 95% and 90%, respectively, with manageable area and performance costs.

O paradigma Network Function Virtualization (NFV) promete tornar as redes de computadores mais escaláveis e flexíveis, através do desacoplamento das funções de rede de hardware dedicado e fornecedor específico. No entanto, funções de rede computacionalmente intensivas podem ser difíceis de virtualizar sem degradação de desempenho. Neste contexto, Field-Programmable Gate Arrays (FPGAs) têm se mostrado uma boa opção para aceleração por hardware de funções de rede virtuais que requerem alta vazão, sem se desviar do conceito de uma infraestrutura NFV que visa alta flexibilidade. A avaliação de expressões regulares é um mecanismo importante e computacionalmente intensivo, usado para realizar Deep Packet Inpection, que pode ser acelerado por FPGA para atender aos requisitos de desempenho. Esta solução, no entanto, apresenta novos desafios em relação aos requisitos de confiabilidade. Particularmente para FPGAs baseados em SRAM, soft errors na memória de configuração são uma ameaça de confiabilidade significativa. Neste trabalho, apresentamos um mecanismo de tolerância a falhas abrangente para lidar com falhas de configuração na funcionalidade de módulos de avaliação de expressões regulares baseados em FPGA. Além disso, é introduzido um mecanismo de correção de erros que considera o posicionamento desses módulos no FPGA para reduzir o tempo de reparo do sistema, melhorando a confiabilidade e a disponibilidade. Os resultados experimentais mostram que a taxa de falha geral e o tempo de reparo do sistema podem ser reduzidos em 95% e 90%, respectivamente, com custos de área e performance admissíveis. / The Network Function Virtualization (NFV) paradigm promises to make computer networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, Field-Programmable Gate Arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for SRAM-based FPGAs, soft errors on the configuration memory are a significant dependability threat. In this work we present a comprehensive fault tolerance mechanism to deal with configuration faults on the functionality of FPGA-based regular expression matching engines. Moreover, a placement-aware scrubbing mechanism is introduced to reduce the system repair time, improving the system reliability and availability. Experimental results show that the overall failure rate and the system mean time to repair can be reduced in 95% and 90%, respectively, with manageable area and performance costs.