The McTronX research group at the North-West University is currently researching self-sensing techniques for Active Magnetic Bearings (AMB). The research is part of an ongoing effort to expand the knowledge base on AMBs in the School of Electrical, Electronic and Computer Engineering to support industries that make use of the technology. The aim of this project is to develop an integrated co-processor based power electronic drive with the emphasis placed on the ability of the co-processor to execute AMB self-sensing algorithms. The two primary techniques for implementing self-sensing in AMBs are state estimation and modulation. This research focuses on hardware development to facilitate the implementation of the modulation method. Self-sensing algorithms require concurrent processing power and speed that are well suited to an architecture that combines a digital signal processor (DSP) and a field programmable gate array (FPGA). A comprehensive review of various power amplifier topologies shows that the pulse width modulation (PWM) switching amplifier is best suited for controlling the voltage and current required to drive the AMB coils. Combining DSPs and power electronics to form an integrated co-processor based power electronic drive requires detail attention to aspects of PCB design, including signal integrity and grounding. A conceptual design is conducted and forms part of the process of compiling a subsystem development specification for the integrated drive, in conjunction with the McTronX Research Group. Component selection criteria, trade-off studies and various circuit simulations serve as the basis for this essential phase of the project. The conceptual design and development specification determines the architecture, functionality and interfaces of the integrated drive. Conceptual designs for the power amplifier, digital controller, electronic supply and mechanical layout of the integrated drive is provided. A detail design is performed for the power amplifier, digital controller and electronic supply. Issues such as component selection, power supply requirements, thermal design, interfacing of the various circuit elements and PCB design are covered in detail. The output of the detail design is a complete set of circuit diagrams for the integrated controller. The integrated drive is interfaced with existing AMB hardware and facilitates the successful implementation of two self-sensing techniques. The hardware performance of the integrated coprocessor based power electronic drive is evaluated by means of measurements taken from this experimental self-sensing setup. The co-processor performance is evaluated in terms of resource usage and execution time and performs satisfactorily in this regard. The integrated co-processor based power electronic drive provided sufficient resources, processing speed and flexibility to accommodate a variety of self-sensing algorithms thus contributing to the research currently underway in the field of AMBs by the McTronX research group at the North-West University. / Thesis (M.Ing. (Electrical Engineering))--North-West University, Potchefstroom Campus, 2009.

Monte Carlo (MC) simulations are widely used in the field of medical biophysics, particularly for modelling light propagation in biological tissue. The iterative nature of MC simulations and their high computation time currently limit their use to solving the forward solution for a given set of source characteristics and tissue optical properties. However, applications such as photodynamic therapy treatment planning or image reconstruction in diffuse optical tomography require solving the inverse problem given a desired light dose distribution or absorber distribution, respectively. A faster means for performing MC simulations would enable the use of MC-based models for such tasks. In this thesis, a gold standard MC code called MCML was accelerated using two distinct hardware-based approaches, namely designing custom hardware on field-programmable gate arrays (FPGAs) and programming commodity graphics processing units (GPUs). Currently, the GPU-based approach is promising, offering approximately 1000-fold speedup with 4 GPUs compared to an Intel Xeon CPU.

The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.

Οι συστοιχίες προγραμματιζόμενων πυλών (FPGAs) αποτελούν μια σημαντική τεχνολογία, η οποία επιτρέπει στους σχεδιαστές κυκλωμάτων την παραγωγή συγκεκριμένου σκοπού ολοκληρωμένων κυκλωμάτων σε σύντομο χρόνο. Tα σημαντικότερα των χαρακτηριστικών τους είναι η αρχιτεκτονική τους και η δυνατότητα σχεδιασμού τους μέσω υπολογιστών, η χαμηλή κατανάλωση ισχύος καθώς και το μικρό χρονικό διάστημα που απαιτείται για τον επαναπρογραμματισμό τους. Τα FPGAs είναι κατάλληλα σχεδιασμένα για ψηφιακές εφαρμογές φιλτραρίσματος. Η πυκνότητα των προγραμματιζόμενων αυτών συστημάτων είναι τέτοια ώστε πολύ μεγάλος αριθμός αριθμητικών πράξεων όπως αυτές που προκύπτουν μέσω ψηφιακού φιλτραρίσματος να μπορεί να εφαρμοστεί σε μία μόνο συσκευή. Τα πλεονεκτήματα των FPGA στην υλοποίηση ψηφιακών φίλτρων είναι μεταξύ άλλων οι υψηλότεροι ρυθμοί δειγματοληψίας από παραδοσιακούς DSP chip, το χαμηλότερο κόστος από μια μέτρια ASIC (Application Specific Integrated Circuit, Kύκλωμα οριζόμενο από εφαρμογή) για εφαρμογές μεγάλου όγκου, καθώς και η μεγαλύτερη ευελιξία από όλες τις εναλλακτικές προσεγγίσεις για την υλοποίηση των FIR φίλτρων. Σπουδαιότερο όλων είναι ότι προγραμματίζονται μέσα στο σύστημα και έχουν δυνατότητα επαναπρογραμματισμού για την υλοποίηση διαφόρων εναλλακτικών λειτουργιών φιλτραρίσματος. Στόχος της παρούσας διπλωματικής είναι να συνδυασθούν τεχνικές VLSI και ψηφιακής επεξεργασίας σήματος και μέσω κατανόησης της αρχιτεκτονικής του υπολογιστή να δημιουργηθεί μια χρήσιμη εφαρμογή. Επιλέχθηκε για τον λόγο αυτό: α) η ανάπτυξη ενός FIR φίλτρου σε γλώσσα περιγραφής υλικού, β) υλοποίησή του σε FPGA, γ) εισαγωγή αυτού σε ενσωματωμένο σύστημα και σύνδεση σε διάδρομο δεδομένων επεξεργαστή και δ) έλεγχος του φίλτρου με τη βοήθεια του επεξεργαστή μέσω γλώσσας υψηλού επιπέδου. Η συγγραφή του κώδικα του φίλτρου έγινε σε γλώσσα VHDL, με structural μεθόδους και η προσομοίωση του συστήματος στο Modelsim. Επιπροσθέτως χρησιμοποιήθηκε ο Project Navigator ISE της Xilinx για τον έλεγχο του κώδικα αλλά και τον προγραμματισμό του FPGA Spartan 3E Starter Board. Χρησιμοποιήθηκαν ακόμα τα υποπρογράμματα Plan Ahead και ChipScope Pro του ISE ώστε να ελεγχθεί η λειτουργία του κυκλώματος στο FPGA. To κύκλωμα τελικά εισάγεται σε ενσωματωμένο σύστημα με τη βοήθεια του εργαλείου σχεδίασης EDK της Xilinx και ελέγχεται η λειτουργία του προγραμματίζοντας τον επεξεργαστή Microblaze. Ακόμα ελέγχεται η λειτουργία του φίλτρου για διαφορετικούς συντελεστές FIR φίλτρων που χρησιμοποιούν διαφορετικά παράθυρα και συγκρίνονται οι «ιδανικές» τιμές που παράγονται από το Matlab με αυτές που παράγονται από το φίλτρο. Τέλος μετράται η ενέργεια (δυναμική και στατική) που καταναλώνεται κατά τη λειτουργία του κυκλώματος στο FPGA με τη βοήθεια του XPower Analyzer. / Field-programmable gate arrays (FPGAs) is a technology of great importance that allows the designers to produce specific purpose integrated circuits in a limited amount of time. The most important of their characteristics are their architecture and the ability of their design with the help of computers, the low power dissipation, as well as the need of a short amount of time to be reprogrammed. FPGAs are properly designed for digital filtering applications. The density of these programmable systems is such that a great amount of numerical calculations such as those that result via digital filtering can be applied to one device only. The advantages of FPGAs as for the implementation of digital filters is between others the great rates of sampling compared to traditional DSP chips, their low cost compared to a moderate ASIC (Application Specific Integrated Circuit) for applications that take up a large area, as well as the flexibility compared to alternative approaches for the implementation of FIR filters. Their most important characteristic is that they can be programmed on-chip and that they have the ability of being reprogrammed for the implementation of different filtering purposes. The aim of this thesis is to combine VLSI techniques and digital signal processing techniques and via the understanding of the computer architecture to create a useful application. To fulfill that purpose: a) a FIR filter was designed with the use of a hardware description language b) the filter was implemented by using an FPGA c) the filter was imported to an embedded system and it was connected to the bus of a microprocessor d) the filter was controlled by the microprocessor via a high-level programming language. The filter was designed using the VHDL language, specifically using structural methods, and its simulation was performed with Modelsim. Also the Project Navigator ISE of Xilinx was used to correct unwanted warnings and to program the FPGA Spartan 3E Starter Board. Some other subprograms of ISE were also used, such as Plan Ahead and ChipScope Pro in order to check the performance of the filter. The circuit is finally imported to an embedded system using the Embedded Developer’s Kit (EDK) of Xilinx. Microblaze was the microprocessor that was used to control the filter’s performance. Additionally, the performance of the filter is checked by using different coefficients of FIR filters by different windowing methods. The ideal values that are produced from Matlab are compared to those of the filter. Finally the power dissipation (static and dynamic) of the filter is measured using XPower Analyzer.

Αντικείμενο της διπλωματικής εργασίας αποτελεί η μελέτη και ανάλυση των μεθόδων διόρθωσης λαθών με χρήση κώδικα BCH που μπορούν να εφαρμοστούν σε συστήματα αποθήκευσης πληροφορίας τεχνολογίας PCM (Phase-Change Memory). Η τεχνολογία PCM αποτελεί μία νέα τεχνολογία που υπόσχεται υψηλές χωρητικότητες, χαμηλή κατανάλωση ισχύος και μπορεί να εφαρμοστεί είτε σε συσκευές αποθήκευσης σταθερής κατάστασης (Solid State Drives) είτε σε μνήμες τυχαίας προσπέλασης (Random-Access Memories), παρέχοντας μία εναλλακτική πρόταση έναντι μνημών τεχνολογίας flash και DRAM. Ένα από τα μειονεκτήματα της τεχνολογίας PCM είναι η ανθεκτικότητα εγγραφής (write endurance), η οποία μπορεί να βελτιωθεί με τη χρήση μεθόδων διόρθωσης λαθών που θα παρατείνουν τον χρόνο ζωής της συσκευής όταν, λόγω της φυσικής φθοράς του μέσου, αρχίσουν να υπάρχουν σφάλματα στα αποθηκευμένα δεδομένα. Για την εφαρμογή της διόρθωσης λαθών μπορούν να χρησιμοποιηθούν κώδικες BCH, οι οποίοι αποτελούν μια κλάση ισχυρών κυκλικών κωδίκων διόρθωσης τυχαίων λαθών, και κατασκευάζονται με χρήση της άλγεβρας πεπερασμένων πεδίων. Οι κώδικες BCH είναι ιδανικοί για διόρθωση λαθών σε συσκευές αποθήκευσης πληροφορίας όπου η κατανομή των λαθών είναι τυχαία. Αρκετοί αλγόριθμοι έχουν προταθεί για τις λειτουργίες αποδοτικής κωδικοποίησης και αποκωδικοποίησης κωδίκων BCH. Στην παρούσα εργασία μελετήθηκαν λύσεις που μπορούν να υλοποιηθούν με παράλληλες αρχιτεκτονικές, ενώ ειδικότερα για την λειτουργία αποκωδικοποίησης έγινε χρήση ενός παράλληλου αλγορίθμου που δεν χρειάζεται αντιστροφείς πεπερασμένου πεδίου για την επίλυση των εξισώσεων των συνδρόμων, επιτυγχάνοντας υψηλές συχνότητες λειτουργίας. Για την κατανόηση των λειτουργιών κωδικοποίησης και αποκωδικοποίησης απαιτείται η προσεκτική μελέτη της άλγεβρας πεπερασμένων πεδίων και της αριθμητικής της. Οι κώδικες BCH προσφέρουν πλεονεκτήματα όπως χαμηλή πολυπλοκότητα και ύπαρξη αποδοτικών μονάδων υλοποίησης σε υλικό. Στην παρούσα εργασία σχεδιάστηκαν ένας παράλληλος κωδικοποιητής και ένας παράλληλος αποκωδικοποιητής για τον κώδικα BCH(728,688). Τα δύο συστήματα υλοποιήθηκαν ως περιφερειακά σε ενσωματωμένο σύστημα βασισμένο σε επεξεργαστή MicroBlaze, με έμφαση σε μια καλή σχέση μεταξύ της συχνότητας λειτουργίας και των απαιτήσεων σε επιφάνεια υλικού και κατανάλωση ισχύος. Για την υλοποίηση χρησιμοποιήθηκε συσκευή FPGA σειράς Virtex-6. / The objective of this thesis is the study and analysis of BCH error-correction methods that can be applied on PCM (Phase-Change Memory) storage devices. PCM is a new technology that promises high capacities, low power consumption and can be applied either on Solid State Drives or on Random Access Memories, providing an alternative to flash and DRAM memories. However, PCM suffers from limited write endurance, which can be increased using error-correction schemes that will extend the lifetime of the device when, due to medium wear-out, errors start to appear in the written data. Thus, BCH codes (powerful cyclic random multiple error-correcting codes) can be employed. BCH codes are ideal for ECC (Error-Correction Coding) in storage devices, due to their fault model which is random noise. Several algorithms have been proposed for the efficient coding and decoding BCH codes. In the present thesis parallel implementations where studied. For the decoding process in particular, a parallel algorithm was used that does not require finite field inverter units to solve the syndrome equations, achieving high operation frequencies. For the understanding of BCH coding and decoding processes, basic knowledge of the finite field algebra and arithmetic is required. BCH codes offer advantages such as low complexity and efficient hardware implementations. In the present thesis a parallel BCH(728,688) encoder and a parallel BCH(728,688) decoder were designed. The above systems were implemented as peripherals on an MicroBlaze-based embedded system, with emphasis on an optimal tradeoff between area and power consumption. A Virtex-6 FPGA device was used for the final stages of the implementation.

Αντικείμενο της παρούσας διπλωματικής εργασίας είναι η παρουσίαση και η μελέτη ενος εναλλακτικού σχεδιασμού του deblocking φίλτρου του προτύπου κωδικοποίησης βίντεο Η.264. Αρχικά επεξηγείται αναλυτικά ο τρόπος λειτουργίας του φίλτρου και στη συνέχεια προτείνεται ένας πρωτοποριακός σχεδιασμός με χρήση pipeline πέντε σταδίων. Ο σχεδιασμός παρουσιάζει σημαντικά πλεονεκτήματα στον τομέα της ταχύτητας (ενδεικτικά εμφανίζεται βελτιωμένη απόδοση στην συχνότητα λειτουργίας και στο throughput). Αυτό πιστοποιήθηκε από μετρήσεις που έγιναν σε συγκεκριμένα fpga και επαλήθευσαν τα θεωρητικά συμπεράσματα που είχαν εξαχθεί. / The standard H.264 (or else MPEG-4 part 10) is nowadays the most widely used standard in the area of video coding as it is supported by the largest enterprises in the internet (including Google, Apple and Youtube). Its most important advantage over the previous standards is that it achieves better bitrate without falling in terms of quality. A crucial part of the standard is the deblocking filter which is applied in each macroblock of a frame so that it reduces the blocking distortion. The filter accounts for about one third of the computational requirements of the standard, something which makes it a really important part of the filtering process. The current diploma thesis presents an alternative design of the filter which achieves better performance than the existing ones. The design is based in the use of two filters (instead of one used in current technology) and moreover, in the application of a pipelined design in each filter. By using a double filter, exploitation of the independence which exists in many parts of the macroblock is achieved. That is to say, it is feasible that different parts of it can be filtered at the same time without facing any problems. Furthermore, the use of the pipeline technique importantly increases the throughput. Needless to say, in order for the desired result to be achieved, the design has to be made really carefully so that the restrictions imposed by the standard will not be failed. The use of this alternative filter design will result in an important raise in the performance. Amongst all, the operating frequency, the throughput and the quality of the produced video will all appear to be considerably risen. It also needs to be mentioned that the inevitable increase of the area used (because of the fact that two filters are used instead of one) is not really important in terms of cost. The structure of the thesis is described in this paragraph. In chapter 1 there is a rather synoptic description of the H.264 standard and the exact position of the deblocking filter in the whole design is clarified. After that, the algorithmic description of the filter follows (Chapter 2). In this chapter, all the parameters participating in the filter are presented in full detail as well as the equations used during the process. In the next chapter (chapter 3), the architecture chosen for the design is presented. That is to say, the block diagram is presented and explained, as well as the table of timings which explains completely how the filter works. The pipelining technique applied in the filter is also analyzed and justified in this chapter. In the next chapter (chapter 4), every structural unit used in the current architecture is analyzed completely and its role in the whole structure is presented. Finally, in chapter 5, the results of the measurements made in typical fpgas of Altera and Xilinx are presented. The results are shown in table format whereas for specific parameters diagrams were used so that the improved performance of the current design compared to the older ones that are widely used, becomes evident.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The development of an integrated avionics system containing all the required sensors and actuators for autopilot control is presented. The thesis analyzes the requirements for the system and presents detailed hardware design. The architecture of the system is based on an FPGA which is tasked with interfacing with the sensors and actuators. The FPGA abstracts a microprocessor from these interface modules, allowing it to focus only on the control and user interface algorithms. Firmware design for the FPGA, as well as a conceptualization of the microprocessor software design is presented. Simulation results showing the functionality of firmware modules are presented. / AFRIKAANSE OPSOMMING: Die ontwikkeling van ‘n geïntegreede avionika‐stelsel wat al die vereiste sensors en aktueerders vir outoloods‐beheer bevat, word voorgestel. Die tesis analiseer die vereistes van die stelsel en stel ‘n hardeware‐ontwerp voor. Die argitektuur van die stelsel bevat ‘n FPGA wat ‘n koppelvlak met sensors en aktueerders skep. Die FPGA verwyder die mikroverwerker weg van hierdie koppelvlak modules en stel dit sodoende in staat om slegs op die beheer en gebruikerskoppelvlak‐algoritmes te fokus. Sagteware‐ontwerp vir die FPGA, asook die konseptualisering van die sagtewareontwerp vir die mikroverwerker, word aangebied. Simulasie resultate wat die funksionaliteit van die FPGA‐sagteware modules aandui, word ook voorgestel.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: Swarm intelligence research was inspired by biological systems in nature. Working ants and bees has captivated researchers for centuries, with the ant playing a major role in shaping the future of robotic swarm applications. The ants foraging activity can be adapted for different applications of robotic swarm intelligence. Numerous researchers have conducted theoretical analysis and experiments on the ants foraging activities and communication styles. Combining this information with modern reconfigurable computing opens the door to more complex behaviour with improved system dynamics. Reconfigurable computing has numerous applications in swarm intelligence such as true hardware parallel processing, dynamic power save algorithms and dynamic peripheral changes to the CPU core. In this research a brief study is made of swarm intelligence and its applications. The ants' foraging activities were studied in greater detail with the emphasis on a layered control system designed implementation in a robotic agent. The robotic agent’s hardware was designed using a partial self reconfigurable FPGA as the main building element. The hardware was designed with the emphasis on system flexibility for swarm application drawing attention to power reduction and battery life. All of this was packaged into a differential drive chassis designed specifically for this project. / AFRIKAANSE OPSOMMING: Die motivering vir swerm robotika kom van die natuur. Vir eeue fassineer swerm insekte soos bye en miere navorsers. Dit is verstommend hoe ’n groep klein en nietige insekte sulke groot take kan verrig. Die mier speel ‘n belangrike rol en is die sentrale tema van menige publikasies. Die mier se kos-soek aktiwiteit kan aangepas word vir swerm robotika toepassings. Hierdie aktiwiteit vervat verskeie sleutel konsepte wat belangrik is vir robotika toepassings. Deur bv. die mier se aktiwiteite te kombineer met dinamies herkonfigureerbare hardeware, kan meer komplekse gedrag bestudeer word. Die stelsel dinamika verbeter ook, aangesien dit nou moontlik is om sekere take in parallel uit te voer. Deur ’n interne prosesseerder in die herkonfigureerbare hardeware in te sluit, is dit nou vir die stelsel moontlik om homself te verander tydens taak verrigting. Komplekse krag bestuur gedrag is ook moontlik deurdat die prosesseerder die spoed en rand apparaat kan verander soos benodig. ‘n Verdere voordeel is dat die stelsel aanpasbaar is en dus vir verskeie navorsingsprojekte gebruik kan word. In hierdie navorsing word ’n literatuur studie van swerm robotika gemaak en word daar ook na toepassings gekyk. Met die klem op praktiese implementering, word die mier se kos-soek aktiwiteit in detail ondersoek deur gebruik te maak van ’n laag beheerstelsel. In hierdie laag beheerstelsel verteenwoordig elke laag ’n hoër vlak gedrag. Stelsel aanpasbaarheid en lae kragverbruik speel ’n deurslaggewende rol in die ontwerp, en om hierdie rede vorm ’n FPGA die hart van die sisteem.

Orientador: Luís Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-16T06:39:32Z (GMT). No. of bitstreams: 1 Okajima_HenriShinichideSouza_M.pdf: 2252019 bytes, checksum: df6b064fa2391bdd5665b43e140c56b1 (MD5) Previous issue date: 2010 / Resumo: Esta dissertação apresenta os resultados obtidos com a pesquisa e implementação de um sistema de demodulação para o receptor de rastreio de um radar de telemedidas. Um radar de telemedidas é responsável pela identificação de um conjunto de medidas realizadas no objeto espacial e enviadas para a antena através de um transponder. A antena de telemedidas deve rastrear o objeto, mantendo-se sempre apontada na direção deste. Para realizar esta função foi utilizada a técnica de monopulso de um canal. Na técnica de monopulso de um canal, cabe ao demodulador digital do receptor executar uma identificação de envoltória e uma demultiplexação temporal que deve permitir encontrar os valores angulares dos erros. A implementação resultou em uma placa de demodulador digital, realizada com um Field Programmable Gate Array (FPGA) da família Cyclone II, e um controlador Freescale, embarcados em uma Placa de Circuito Impresso (PCI) de quatro camadas, projetada para interfacear sinais digitais para controle do sistema de telemedidas e para condicionar os sinais analógicos para posterior processamento. Além de ter interface com placas específicas (por exemplo, CAF - Controle automático de freqüência, CAG - controle automático de ganho, Gerador de Teste, etc), possui também uma interface Controller Area Network (CAN) para comunicação com os módulos de controle de servomecanismos da antena e de interface usuário. Foi desenvolvido também um ambiente de simulação para o demodulador digital em Matlab permitindo verificar a coerência com os resultados esperados e traçar cenários de testes / Abstract: This project presents the results obtained by the research and development of a Demodulation System for a telemetry radar tracking receiver. A telemetry radar system is responsible for identifying a set of measures taken from a spatial artifact and is transmitted by a transponder to its antenna. The telemetry antenna must track the spatial object, maintaining the antenna pointing in the correct direction. To execute this function a single channel monopulse technique is applied. Since the single channel monopulse technique is used, a digital demodulator task is then run for amplitude identification and the de-multiplexing time frame must occur in order to calculate the angle values of errors. This process is explained during the dissertation after the presentation of the main characteristics of radars and some aspects of telemetry systems. The solution is a digital demodulator electronic board, build with an FPGA (Field Programmable Gate Array) from Altera Cyclone II® family, and a Freescale® controller, over a multilayer PCB (Printed Circuit Board) projected to interface with digital signals for the Telemetry Control System and to conditioning analogical signals for processing tasks. The developed board has the CAN (Controller Area Network) interface to communicate with the servomechanism control modules associated with the Antenna and is placed in an armored drawer - to avoid electromagnetic noises - as well as to interact with other specific board functions.A simulation environment was achieved for the digital demodulator in Matlab, allowing the results verification and allowing to establish others testing scenarios / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Orientadores: João Marcos Travassos Romano, Cynthia Cristina Martins Junqueira / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-17T17:05:38Z (GMT). No. of bitstreams: 1 ChinattoJunior_AdilsonWalter_M.pdf: 7887281 bytes, checksum: 23d4e34e4a2b77a46e1707773d7b5fdf (MD5) Previous issue date: 2011 / Resumo: O Processamento Largamente Linear, desenvolvido durante a década de 1990, tem levado a uma melhoria no desempenho de algoritmos adaptativos para determinadas situações que empregam sinais impróprios. Quando aplicado a arranjos de antenas, esse tipo de processamento apresenta a potencialidade ser mais robusto e eficiente que as técnicas clássicas de filtragem. Dessa forma, este trabalho busca estender uma série de algoritmos adaptativos clássicos de conformação de feixe para a forma largamente linear, verificando através de simulações os eventuais ganhos em desempenho obtidos na tarefa de mitigação de interferentes através de arranjos de antenas. São avaliados algoritmos treinados, com restrições e cegos, cobrindo um leque relativamente amplo de cenários de utilização. Visando o uso de arranjos de antenas em cenários em que os sinais incidentes possuam modulação real, são propostas otimizações para os algoritmos largamente lineares que levam a uma redução da complexidade computacional, mantendo o desempenho do algoritmo original. Essas otimizações são aplicadas para algoritmos treinados, com restrições e cegos, sendo seus desempenhos comparados através de simulações com os desempenhos obtidos através dos algoritmos largamente lineares originais e dos algoritmos estritamente lineares. Por fim, uma plataforma para testes de arranjos de antenas é implementada em hardware provido de dispositivo de lógica programável (FPGA), permitindo que sejam realizados ensaios práticos envolvendo caracterização de antenas, conformação de feixe não adaptativa e mitigação de interferentes através de algoritmos adaptativos / Abstract: Widely Linear Processing, developed during the 1990s, has led to an improved performance of adaptive algorithms under certain situations that involve improper signals. When applied to antenna arrays, this type of processing shows to be potentially more robust and efficient than the classical filtering techniques. The objective of this work is to extend several classic adaptive beamforming algorithms to the widely linear form, verifying by means of simulations the potential gains in performance when applied to the task of mitigating interference in antenna arrays. Trained, restricted and blind algorithms are considered, covering a relatively broad range of feasible scenarios. Addressing the use of antenna arrays in scenarios in which the incident signals involved have real modulation, optimizations for the widely linear algorithms are proposed, thereby promoting reductions in the computational complexity, while maintaining the original algorithm performance. These optimizations are applied to trained, restricted and blind algorithms, and their performance is compared through simulations with the performances obtained using the original algorithms in their largely linear and strictly linear versions. Finally, an antenna array test platform is implemented in the hardware, allowing practical tests to be carried out. A set of measures taken with the antenna array test platform is exhibited, which include characterization of antennas, non-adaptive beamforming and interference mitigation using adaptive algorithms / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica