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This letter investigates the impact of self-heating on the post-cycling functionality of a scaled hafnium oxide-based ferroelectric field-effect transistor (FeFET). The full recovery of FeFET switching properties and data retention after the cycling endurance failure is reported. This is achieved by damage annealing through localized heating, which is intentionally induced by a large current flow through the drain (source)-body p-n junctions. The results highlight that the local thermal treatments could be exploited to extend the cycling endurance of FeFETs.

Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal-oxide-semiconductor field-effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF-ratio in today's integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor and Ge heterostructures further improve the ON-state current and reduce SS due to the low bandgap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y and Ge/InxGa1-xAs heterostructures allow a wide range of bandgap energies and various band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the InxGa1-xAs or GaAsySb1-y. In particular, this research systematically investigate the development and optimization of low-power TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures including: basic working principles, design considerations, material growth, interface engineering, material characterization, band alignment determination, device fabrication, device performance investigation, and high-temperature reliability. A comprehensive study of TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures shows superior structural properties and distinguished device performances, both of which indicate the mixed As/Sb and Ge/InxGa1-xAs based TFET as a promising option for high performance, low standby power and energy efficient logic circuit application. / Ph. D.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed. / Master of Science / According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

Dans le domaine de l’électronique de puissance, les dispositifs en carbure de silicium (SiC) sont bien adaptés pour fonctionner dans des environnements à haute température, haute puissance, haute tension et haute radiation. Le carbure de silicium (SiC) est un matériau semi-conducteur à large bande d’énergie interdite. Ce matériau possède des caractéristiques en température et une tenue aux champs électriques bien supérieure à celles de silicium. Ces caractéristiques permettent des améliorations significatives dans une grande variété d’applications et de systèmes. Parmi les interrupteurs existants, le JFET en SiC est l’interrupteur le plus avancé dans son développement technologique, et il est au stade de la pré-commercialisation. Le travail réalisé au cours de cette thèse consiste à caractériser électriquement des JFET- SiC de SiCED en fonction de la température (25°C-300°C). Des mesures ont été réalisé en statique (courant-tension), en dynamique (capacité-tension) et en commutation sur charge R-L (résistive-inductives) et dans un bras d’onduleur. Un modèle multi-physique du transistor VJFET de SiCED à un canal latéral a été présenté. Le modèle a été développé en langage MAST et validé aussi bien en mode de fonctionnement statique que dynamique en utilisant le simulateur SABER. Ce modèle inclut une représentation asymétrique du canal latéral et les capacités de jonction de la structure. La validation du modèle montre une bonne concordance entre les mesures et la simulation. / In the field of power of electronics, silicon carbide (SiC) devices are well suited to operate in environments at high temperature, high power, high voltage and high radiation. The silicon carbide belongs to the class of wide band gap semiconductor material. Indeed, this material has higher values than the silicon ones for the temperature breakdown and a high electric field breakdown. These characteristics enable significant improvements in wide varieties of applications and systems. Among the existing switches, SiC JFET is the most advanced one in its technological development because it is at the stage of pre-marketing. The study realized during this thesis was to electrically characterize SiC JFETs from SiCED versus the temperature (25°C-300°C). The characteristic are based on static measurements (currentvoltage), capacitive measurements (capacitive-voltage) and switching measurements in an R-L (resistor-inductor) load circuit and an inverter leg. A multi-physical model of the VJFET with a lateral channel is presented. The model was developed and validated in MAST language both in static and dynamic modes using the SABER simulator. The model includes an asymmetric representation of the lateral channel and the junction capacitances of the structure. The validation of the model shows a good agreement between measurements and simulation.

The work presented in the thesis is focused on the synthesis of diverse colloidal semiconductor NCs in organic media, their surface design with tiny inorganic and hybrid capping species in solution phase, and subsequent assembling of these NC building units into two-dimensional close-packed thin-films and three-dimensional non-ordered porous superstructures.

An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.

The work presented in the thesis is focused on the synthesis of diverse colloidal semiconductor NCs in organic media, their surface design with tiny inorganic and hybrid capping species in solution phase, and subsequent assembling of these NC building units into two-dimensional close-packed thin-films and three-dimensional non-ordered porous superstructures.

Durch Multiskalensimulationen wird der Ladungstransport in nanodrahtbasierten Schottky-Barrieren-Feldeffekt-Transistoren im Materialsystem Ni2Si/Si untersucht. Die Bedingungen an die Genauigkeit der verwendeten Eingangsparameter werden bestimmt und Vorhersagen über optimale Material- und Geräteparameter werden getroffen. Es wird die Frage beantwortet, ob die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinie möglich ist. Der Feldeffekt wird durch Berechnungen auf Basis der Finiten-Elemente-Methode und die resultierenden Stromflüsse durch ein quantenmechanisches Transportmodell ermittelt. In der Untersuchung der geometrischen Eingangsparameter wird gezeigt, dass bis auf den Radius des Nanodrahtes die in einem Experiment zu erwartenden Messfehler keinen drastischen Einfluss auf die Strom-Spannungs-Kennlinie haben. Signifikant ist hingegen der Einfluss der Temperatur, der effektiven Ladungsträgermassen und der Höhe der Schottky-Barriere. Da diese drei Eingangsparameter des betrachteten Systems mit relativ großen Ungenauigkeiten behaftet sind, ist die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinien auf die erhoffte Weise nicht möglich. Die Arbeit zeigt auch, dass bereits moderate Veränderungen der Arbeitstemperatur einen bedeutenden Einfluss auf die Strom-Spannungs-Kennlinie haben. Für die Konstruktion von Transistoren mit hoher Stromdichte kann anhand der ermittelten Daten die Verkleinerung der aktiven Region durch Oxidation vorgeschlagen werden.:Kurzfassung/Abstract I Verwendete Symbole IV Verwendete Parameter VI Verwendete Abkürzungen VII 1 Motivation 8 2 Grundlagen 9 2.1 Modellbildung und Simulation 9 2.2 Schottky-Diode 10 2.3 Feldeffekt-Transistor 12 2.4 Feldeffekt-Transistor auf der Basis von Silizium-Nanodrähten 13 3 Methoden 17 3.1 Simulationsmodell 17 3.2 Finite-Elemente-Methode 20 3.3 Landauer-Büttiker-Formalismus 21 3.4 Hamiltonoperator 22 3.5 Transmissionsfunktion 23 3.6 Büttiker Sonde 24 4 Ergebnisse und Diskussion 26 4.1 Implementierung des Simulationsprogrammes 26 4.2 Berechnung der Basis-Strom-Spannungs-Kennlinie 31 4.3 Wahl der Simulationsparameter 35 4.4 Abhängigkeit von geometrischen Parametern 41 4.5 Abhängigkeit von physikalischen Parametern 49 5 Zusammenfassung, Schlussfolgerungen und Ausblick 55 Abbildungsverzeichnis 59 Literatur 62 / Charge transport in nanowire-based Schottky-barrier field-effect transistors in the material system Ni2Si/Si is examined by multi-scale simulations. The requirements for the accuracy of the input parameters are determined and predictions about optimum material and device parameters are made. The question is answered, whether the determination of physical parameters from individual measured current-voltage curves is possible? The field effect is described by calculations based on the finite element method and the resulting currents are calculated with a quantum mechanical transport model. In the study of the geometric input parameters it is shown that experimental uncertainties do not drastically affect the current-voltage characteristic, except from the nanowire radius. However, significant is the influence of the temperature, the effective charge carrier mass and the height of the Schottky-barrier. Since these three input parameters are known only with low experimental accuracy for the considered system, the determination of physical parameters from individual measured current-voltage curves is not possible in the expected way. The results also show that moderate changes of the working temperature have a significant influence on the current-voltage characteristic. For the construction of transistors with high current density the reduction of the active region by oxidation is proposed.:Kurzfassung/Abstract I Verwendete Symbole IV Verwendete Parameter VI Verwendete Abkürzungen VII 1 Motivation 8 2 Grundlagen 9 2.1 Modellbildung und Simulation 9 2.2 Schottky-Diode 10 2.3 Feldeffekt-Transistor 12 2.4 Feldeffekt-Transistor auf der Basis von Silizium-Nanodrähten 13 3 Methoden 17 3.1 Simulationsmodell 17 3.2 Finite-Elemente-Methode 20 3.3 Landauer-Büttiker-Formalismus 21 3.4 Hamiltonoperator 22 3.5 Transmissionsfunktion 23 3.6 Büttiker Sonde 24 4 Ergebnisse und Diskussion 26 4.1 Implementierung des Simulationsprogrammes 26 4.2 Berechnung der Basis-Strom-Spannungs-Kennlinie 31 4.3 Wahl der Simulationsparameter 35 4.4 Abhängigkeit von geometrischen Parametern 41 4.5 Abhängigkeit von physikalischen Parametern 49 5 Zusammenfassung, Schlussfolgerungen und Ausblick 55 Abbildungsverzeichnis 59 Literatur 62

L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canal.