The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown

International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a Packet Processor card utilizing semi-custom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multi-channel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the Packet Processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semi-custom VLSI logic.

No description available.

In the Λ-system, non-adiabatic holonomic quantum phases are used to construct holonomic quantum gates. An interesting approach would be to implement open path holonomies in the Λ-system. By dividing the loop into two curve segments with a unitary transformation between them, universality can be reached. In doing so the exibility of the scheme has been increased by the fact that one single full pulse is now enough for universality, and we have achieved a clearer proof of the geometric property of the Λ system. / I ett Λ-system så används icke-adiabatiska holonoma kvantfaser för att bygga holonoma kvantgrindar. I detta arbete undersöker vi om holonomier för öppna kurvor kan implementeras i Λsystemet. Genom att dela upp en loop i Λ-systemet i två sekvenser med en unitär transformation emellan så kan vi konstruera en universell holonom kvantgrind. Med detta så har vi ökat exibiliteten för systemet genom att vi nu bara behöver ta en loop för att nå universalitet, och vi har även erhållit en klarare bild över den geometriska egenskapen hos Λ-systemet.

No description available.

No description available.

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

A novel gate driver design is proposed to improve the conversion efficiency of DC-DC converters. Conventional gate drivers provide a fixed gate driving strength (capability) over the entire output load range. However, it is demonstrated that to optimize the overall conversion efficiency, the driving capability of the gate driver circuit should be adjusted according to the loading condition. The proposed segmented gate driver consists of 8 parallel driver segments that can be turned on/off allowing the power consumption of the gate driver circuit to be dynamically adjusted. The post layout simulation results in high voltage TSMC 0.25µm CMOS process shows that up to 7% improvement in the efficiency can be achieved. Furthermore, in addition to efficiency improvements, a 60% reduction in the ringing and overshoot/undershoot was observed. An integrated segmented gate driver IC designed for AMSP35HV process was submitted for fabrication with the support from CMC.

A novel gate driver design is proposed to improve the conversion efficiency of DC-DC converters. Conventional gate drivers provide a fixed gate driving strength (capability) over the entire output load range. However, it is demonstrated that to optimize the overall conversion efficiency, the driving capability of the gate driver circuit should be adjusted according to the loading condition. The proposed segmented gate driver consists of 8 parallel driver segments that can be turned on/off allowing the power consumption of the gate driver circuit to be dynamically adjusted. The post layout simulation results in high voltage TSMC 0.25µm CMOS process shows that up to 7% improvement in the efficiency can be achieved. Furthermore, in addition to efficiency improvements, a 60% reduction in the ringing and overshoot/undershoot was observed. An integrated segmented gate driver IC designed for AMSP35HV process was submitted for fabrication with the support from CMC.

Recognition and sensing of ions is an important front in supramolecular organic chemistry. One remarkable extension of this kind of work is the application of selective switching processes to logic gate operations. In this study, we have designed selective metal ion chelators for zinc and cadmium ions based on dansylamide fluorophores and dipicolylamine chelators. The zinc complex of a previously reported difluoroboradiazaindacene-bipyridyl derivative was shown to respond anions by an increase in emission intensity. We also discovered a hitherto unknown reaction of difluoroboradiazaindacenes and showed that this reaction can be exploited in a very selective sensing of fluoride ions in acetone solutions. The remarkable chemistry of these boradiazaindacene dyes, especially the bipyridyl derivative, allowed us to propose the first example of a unimolecular &ldquo / molecular subtractor&rdquo / . A single molecule can carry out substraction of binary inputs, when these inputs are fluoride anion and zinc cation.