Analog Computing Arrays (ACAs) provide a computation system capable of performing a large number of multiply and add operations in an analog form. This system can therefore implement several computation algorithms that are currently realized using Digital Signal Processors (DSPs) who have an analogues accumulate and add functionality. DSPs are generally preferred for signal processing because they provide an environment that permits programmability once fabricated. ACA systems propose to offer similar functionality by providing a programmable and reconfigurable analog system. ACAs inherent parallelism and analog efficiency present several advantages over DSP implementations of the same systems. The computation power of an ACA system is directly proportional to the number of computing elements used in the system. Array size is limited by the number of computation elements that can be managed in an array. This number is continually growing and as a result, is permitting the realization of signal processing systems such as real-time speech recognition, image processing, and many other matrix like computation systems. This research provides a systematic process to implement, program, and use the computation elements in large-scale Analog Computing Arrays. This infrastructure facilitates the incorporation of ACA without the current headaches of programming large arrays of analog floating-gates from off-chip, currently using multiple power supplies, expensive FPGA controllers/computers, and custom Printed Circuit Board (PCB) systems. Proof of the flexibility and usefulness of ACAs has been demonstrated by the construction of two systems, an Analog Fourier Transform and a Vector Quantizer.

Abstract In this thesis, we propose and fabricate a triple recessed multi-gate SOI device that has high transconductance and low series resistance. The SOI device structure has three unique features. First, it uses mesa isolation instead of using conventional LOCOS and trench isolation to avoid the bird¡¦s beak effect in LOCOS isolation and the complexity of digging trench in trench isolation. Second, it combines the rounded and gate recessed structure to reduce the edge effect and lower the source/drain parasitic resistance. Third, it has three surfaces of gate structure that can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the integrated circuit. From our experiment results the trends of device characteristics exhibits good agreement with the 3 ¡V D simulation results. According to the simulation results of 3 ¡V D DAVINCI and the measurement results, triple recessed multi-gate SOI MOSFET¡¦s presents four unique characteristics, which are superior to conventional SOI with the same device parameter in deep sub-micrometer regime. First, multi-gate SOI has better short channel effect and drain induce barrier lowing immunity conventional SOI device than conventional SOI device. Second, it has higher transconductance and higher current drive capability. Third, the breakdown voltage is higher than that of conventional SOI device. Fourth, self-heating effect would not increase with current gain increase, triple recessed multi-gate SOI device has better self-heating effect immunity. These four advantages show the triple recessed multi-gate SOI MOSFET¡¦s is suitable for high speed and low power applications along shrink of device dimensions.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 212-225). Available also in a digital version from Dissertation Abstracts.

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With rapid progress in microelectronics technology, high-performance Integrated Circuits (ICs) bring huge challenge to design the power supplies. Fast loop response is required to handle the high transient current of devices. Power solution size is demanded to reduce due to the size reduction of integrated circuits. The best way to meet these harsh requirements is to increase switching frequency of power supplies. Along with the benefits of increasing switching frequency, the power supplies will suffer from high switching loss and high gate charge loss as these losses are frequency dependant losses. This thesis investigates the best topology to minimize the switching loss. The Series-Parallel Resonant Converter (SPRC) with current-doubler is mainly analyzed for high frequency low voltage high current application. The advantages and disadvantages of SPRC with current-doubler are presented. A new adaptive synchronous rectifiers timing control scheme is also proposed. The proposed timing control scheme demonstrates it can minimize body diode conduction loss of synchronous rectifiers and therefore improve the efficiency of the converter. This thesis also proposes two families of new resonant gate drive circuits. The circuits recover a portion of gate drive energy that is total lost in conventional gate drive circuit. In addition to reducing gate charge loss, it also reduces the switching losses of the power switches. Detail operation principle, loss analysis and design guideline of the proposed drive circuits are provided. Simulation and experimental results are also presented. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-01-29 22:37:09.812

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Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. / Thesis (PhD)--University of South Australia, 2005.