Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

Mannheim, Univ., Diss., 2006.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Glasgow, 2003. / Includes bibliographical references. Print version also available.

Quantum computers offer great potential for significant speedup in executing certain algorithms compared to their classical counterparts. One of the most promising physical systems in which implementing such a device seems viable are trapped atomic ions. All of the fundamental operations needed for quantum information processing have already been experimentally demonstrated in trapped ion systems. Today, the remaining two obstacles are to improve the fidelities of these operations up to the point where quantum error correction techniques can be successfully applied, as well as to scale up the present systems to a higher number of quantum bits (qubits). This thesis addresses both issues. On the one hand, it decribes the experimental implementation of a high-fidelity two-qubit quantum logic gate, which is the most technically demanding fundamental operation to realise in practice. On the other hand, the presented work is carried out in a microfabricated surface ion trap - an architecture that holds the promise of scalability. The gate is applied directly to hyperfine "atomic clock" qubits in ⁴³Ca⁺ ions using the near-field microwave magnetic field gradient produced by an integrated trap electrode. To protect the gate against fluctuating energy shifts of the qubit states, as well as to avoid the need to null the microwave field at the position of the ions, a dynamically decoupled Mølmer-Sørensen scheme is employed. After accounting for state preparation and measurement errors, the achieved gate fidelity is 99.7(1)%. In previous work, the same apparatus has been used to demonstrate coherence times of T^*₂ ≈ 50 s and all single-qubit operations with fidelity > 99.95%. To gain access to the "atomic clock" qubit transition in ⁴³Ca⁺, a static magnetic field of 146G is applied. The resulting energy level Zeeman-structure is spread over many times the linewidth of the atomic transition used for Doppler cooling. This thesis presents a simple and robust method for Doppler cooling and obtaining high fluorescence from this qubit in spite of the complicated level structure. A temperature of 0.3mK, slightly below the Doppler limit, is reached.

No description available.

PhD Thesis / Recently, gallium nitride high electron mobility transistor [GaN HEMT] has evolved as a promising device in the field of power electronics. It has excellent material qualities such as high bandgap, high saturation velocity, and good thermal stability which is expected to give superior device performances compared to its Si counterparts. One of the major challenges in GaN technology is to achieve enhancement operation (or normally off mode) due to the presence of its inherent two-dimensional electron gas[2DEG]. Among many methods developed to realize this, pGaN HEMT has emerged as the most encouraging technique for power GaN technology due to its high threshold voltage and good reliability. However, one of the major issues in pGaN HEMTs is that it suffers from high gate leakage current which limits their device performance. In this thesis, we have made a detailed study of the gate leakage process in pGaN HEMTs in terms of modeling, TCAD simulations, and alternative methods being used to reduce gate leakage in pGaN devices. A numerical model has been developed to model the gate leakage in pGaN HEMTs as a function of gate bias and temperature. This model is validated against 5 devices with different contact metals, geometries, and process conditions. A single model with a consistent set of parameters can fit the experimental data for all these 5 devices without the need to invoke multiple mechanisms to explain the gate leakage process. The numerical model relied on some simplifications, such as ignoring series resistance, using the compact diode model, and using a simplified expression to describe trap-assisted tunneling. Using commercial TCAD simulations, can address these limitations since the simulator computes the electric field distribution throughout the structure. Furthermore, using TCAD some of the trap levels have been identified which accounts for leakage at low bias. We were able to calibrate our TCAD simulations against published data for the drain current and then used the calibrated simulation environment to accurately simulate gate leakage using parameters that closely correspond to the physical phenomena described, including interface trap parameters, which we identify with known trap levels in GaN. Finally, we have examined different strategies that have been implemented so far to reduce leakage current. The pGaN layer is important in the whole device operation. Its doping concentration and thickness affect the leakage characteristics. Three modified structures have been studied through TCAD simulations which decrease gate leakage current. In each case, we used our calibrated TCAD model to study the impact on the drain current as well as the leakage current. Our results closely fit published experimental results and therefore provide confidence on the simulated dependence of leakage and drive current behavior on process modifications. The specific results, and our model overall, are expected to be of benefit to device designers in optimizing device structures for leakage while maintaining the required drive current. / Thesis / Doctor of Philosophy (PhD)

This thesis examines a floating gate device (FGD) structure available under standard (digital) CMOS manufacturing processes and puts forth two applications for these devices. The first application is the creation of a tunable current mirror. Inclusion of the FGD structure allows the legs of the mirror to be electronically tweaked to compensate for mismatch. Experimental data is presented on this device structure?s performance. The second application explores using the FGD structure as a tunable resistor. Operation of the FGD in this manner creates the possibility of an electrically tunable beta-multiplier current reference. This tunability allows theoretical adjustment of both the generated reference current as well as a selectable temperature performance. Experimental data of obtained resistor values is presented with simulation results of the entire circuit.

No description available.

No description available.