The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer. / Singapore-MIT Alliance (SMA)

In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we divide the thesis into two parts, strained-silicon channel engineering and high-k/metal gate stacks respectively. Firstly, to study the influence of stress on carrier transport properties, we proposed an approach to get uniaxial compressive/tensile stress from the channel by bending silicon substrate to enhance device performance. By applying uniaxial longitudinal tensile/compressive stress, the drain current and mobility were found to increase obviously in n/p-type MOSFETs, respectively. The enhancement can be attributed to the reduction of effective transport mass and to the suppression of inter-valley scattering. However, we found that the external mechanical stress aggravated hot carrier effects in n-type MOSFETs. Therefore, in n-type MOSFETs, the behaviors of the substrate current and the impact ionization rate under mechanical stress are investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current has significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the band gap. In p-type MOSFETs, the reliability issue, named negative bias temperature instability, is the dominant degradation mechanism during ON-state operation. Therefore, we investigate the NBTI characteristics of strained p-type MOSFETs with external uniaxial tensile/compressive stress. The results indicate that uniaxial compressive stress not only enhances drive current but also reduces NBTI degradation. On the contrary, uniaxial tensile stress leads to a significant degradation in both of drive current and NBTI behavior. The observed Cgc-Vg curve shows the inversion capacitance is strongly dependent on mechanical strain, meaning that the probability of electrochemical reaction decreases/or increases due to the changes in inversion carrier density according to the Nit generation rate of the reaction-diffusion model. Moreover, the charge pumping result is also consistent with the threshold voltage shift of the strained device, which means the degradation is mainly due to trap generation at the Si/SiO2 interface. In addition, to investigate the influences of biaxial compressive stress on p-MOSFETs, we attempts to combine intrinsic and external mechanical stress. It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised Source/Drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature. However, this phenomenon was inverted above 363K. Because hole can gain enough thermal energy to transit to higher energy level by inter-valley scattering, its transport mechanism was dominated by lower effective mass at higher energy level. Besides, the model is also evidenced that the mobility degradation under biaxial compressive stress becomes aggravated while temperature decreases from 300 K to 100 K, which is mainly due to the increase of the ratio of carriers occupied in lowest band. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 65 nm technology node due to unacceptable gate leakage current. Therefore, in the second section of this thesis, we established the electrical characteristics and physical mechanisms of MOSFETs with HfO2 dielectric/TiN gate by analyzing experimental data from charge pumping, split C-V, DC Id-Vg, and pulse Id-Vg. It is found that the threshold voltage (Vth) has a significant decrease as titanium increases in metal gate for n-MOSFETs, whereas the Vth increases in p-MOSFETs. By examining flat band voltage, we found the Vth shift was resulted from metal gate work function (£pm) which became smaller as titanium increased in metal gate. In addition,the dependence of effective mobility on temperature from 100K to 300K was entirely analyzed, which indicated HfO2 remote phonon scattering as the dominant cause of the mobility degradation in n- and p-type MOSFETs when titanium decreased. However, the gate leakage current is also strongly dependent on the nitrogen in metal gate. It is proved that the nitrogen can assivate the traps in HfO2 by pulse I-V,leading to the decrease in gate leakage dominated by Frenkel- Poole mechanism.

Electronic devices such as high power devices, microprocessors and memories in integrated circuit are primarily composed of metal-oxide-semiconductor field effect transistors (MOSFETs), due to the advantages of low cost, low power consumption and easy to scale down. However, the aggressively scaled conventional MOS devices have suffered remarkable short channel effects such as drain induced barrier lowering, punch-through, and direct-tunneling gate leakage. These problems not only lower the gate controllability but also increase the standby power consumption. Because the SiO2 dielectric and poly-gate are improper for CMOS application below 45 nm technology node due to the critical gate leakage current. Therefore, we investigate the electrical characteristics and physical mechanisms of MOSFETs with HfO2/TixN1-x gate stacks by using split C-V, pulsed Id-Vg, and charge-pumping techniques. The experimental results indicate that dynamic stress is more serious than static stress, and hot-carrier effect corresponding to different gate stress biases demonstrate distinct dominant degradation behaviors and the charge-trapping phenomenon. Furthermore, different concentration of titanium in TiN metal gate significantly affect device characteristics associated with the amount of nitrogen diffusion from the metal gate to high-k bulk and the SiO2/Si interface layer.

For the high performance integrated circuits applications such as microprocessors, memories and high power devices, the metal-oxide-semiconductor field effect transistors (MOSFETs) is the most important device due to its low cost, power consumption and scalable property especially. However, the aggressive scaling of conventional MOS devices suffered from noticeable short channel effects such as drain induction barrier lower, punch through, and direct tunneling gate leakage. Those problems not only lower the gate control ability but also increase the standby power consumption. For future VLSI devises below 65 nm regimes, silicon-on-insulator (SOI) and high-k/metal gate MOSFETs are considered to be possible candidates because of faster operation speed and lower power consumption. Therefore, this dissertation investigates the electrical characteristics and reliability issues of novel MOSFETs for 65 nm and below technology. It is roughly divided into two parts, partially depleted (PD) SOI MOSFETs and high-k/metal gate stack MOSFETs, respectively. In the first part, we systematically investigate the mechanism of gate-induced floating body effect (GIFBE) for advanced PD SOI n-MOSFETs. Based on different operation conditions, it was found that the dominant mechanism can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron-valence band (EVB) tunneling. Analyzing the GIFBE in different temperature provides further evidence that the accumulation of holes in the body results from the AHI induced direct tunneling current from the poly-Si gate. In addition, we proposed an approach by bending silicon substrate to further study the impact of mechanical strain on GIFBE. The experimental result indicates that the strain effect indeed decreases the gate leakage current, but increases the hole-valence band (HVB) tunneling current, which indicates that GIFBE becomes serious under mechanical strain. Based on our proposed AHI model, this phenomenon can be mainly due to strain-induced band gap narrowing in the poly-Si gate. In p-type MOSFETs, the reliability issue, named negative bias temperature instability (NBTI), is the dominant degradation mechanism during ON-state operation. Therefore, we also investigate the GIFBE on NBTI degradation for PD SOI p-MOSFETs. The experimental results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ poly gate. However, based on different operation conditions, we found the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. Therefore, we propose the anode electron injection (AEI) model, similar to anode hole injection model, to explain how this main electron origin is generated during the NBTI stress. Finally, based on our proposed model, we further study influence of mechanical strain on GIFBE for SOI p-MOSFETs. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 45 nm technology node due to unacceptable gate leakage current. Therefore, in the second part of this thesis, we investigate the electrical characteristics and physical mechanisms for MOSFETs with HfO2/TixN1-x stacks by using split C-V, DC Id-Vg, and charge pumping techniques. The experimental results indicates that different ratio of Ti strongly affect various parameters, including threshold voltage, mobility, and subthreshold swing, respectively. In addition, the gate leakage current is also strongly dependent on the nitrogen in metal gate. By charge pumping technique, it was found that with increasing Ti concentration of metal gate, there is a trade-off relationship among the interface traps and bulk defects of high-k dielectric. This phenomenon is associated with the amount of nitride diffusion from the metal gate to high-k bulk and SiO2/Si interface layer. In the aspects of reliability, charge trapping in high-k gate stacks remains an important issue since it causes the threshold voltage (Vth) shift and drive current degradation. This phenomenon can be attributed to a large number of pre-existing traps in the high-k dielectric layer. In real circuit operation, the devices are generally operated in the dynamic condition. Therefore, the following study further investigates Vth instability of Hf-based n-MOSFETs under the dynamic bias operation. The static condition was also performed on the identical device for a comparison. The results indicate threshold voltage (Vth) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. In addition, the Vth shift clearly increases with an increase in dynamic stress operation frequency. According to these experimental results, we propose a possible physical model for electron trapping phenomena under dynamic stress. Based on our proposed model, we further dynamic stress induced charge trapping characteristics for devices with different Ti1-xNx composition of metal-gate electrodes. In addition, we further respectively investigates the temperature dependence of dynamic positive bias stress (PBS) and negative bias stress (NBS) degradation in n-type and p-type MOSFETs with high-k/metal gate stacks. The experimental results indicate there is a contrary trend in temperature dependence of Vth shifts for n- and p-MOSFETs under dynamic PBS and NBS, respectively. The Vth shift decreases with increasing temperature for n-MOSFETs under dynamic PBS. This is due to the thermal emission of trapped electrons in high temperature, leading to the reduction in. A contrary trend with temperature for p-MOSFETs under dynamic NBS can be attributed to the interface trap generation induced by NBTI. On the other hand, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability concern in device scaling. However, the stress-induced drain leakage current degradation in device with high-k/metal gate stacks has not received as much attention. In fact, the GIDL behavior is associated with phenomenon of charge trapping in high-k dielectric layer. Therefore, the final study is to investigate the effects of channel hot carrier stress (CHCS) on the gate-induced drain leakage current (GIDL) for n-MOSFETs with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the IGIDL after CHCS, and observed that the magnitude of IGIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric.

Many efforts have been conducted for improving the operation and management of open channel networks. Implementing simulation models and software is an effective step in achieving better operation of control structures in open channel networks. The purpose of this study was to develop a tool in ArcGIS for assisting the open channel network managers in operating flow control structures. This model presents a time schedule for gate operation based on the demands at turnouts through the water usage schedule of the network. The developed model was designed to be added as a tool to ArcToolbox in ArcGIS. Any ArcGIS user who has access to ArcView or ArcInfo can add this tool to ArcToolbox. Using ArcGIS Geoprocessing tools, ModelBuilder, Scripting and ArcToolbox tools, the proposed model, "Arc-Canal", was created. Arc-Canal is implementable for irrigation networks that open channel network are digitized in ArcGIS. Simulation is for the gravity flow in open channels without any pump in the network. Calculations are based on steady flow. All hydraulic calculations for water level, gates, and weirs are based on the methods defined in "Open-Channel Hydraulics" (Chow 1959). Most of the available flow simulation models are complicated individual software for which user needs to be trained to install and use it. Also most of these software are not free accessible. Arc-Canal is an easy to use tool that anyone with the knowledge of working with ArcGIS can run it. By adding the tool to ArcToolbox and following the described naming method, and entering the required data, model is ready to run. The developed model is a free access tool. Most of the channels in open channel networks in south Texas have mild bottom slope and flow is steady gravity flow. It is desired that the developed model will be a tool to assist irrigation districts in south Texas.

In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability in performance and power consumption of an IC, which affects the overall yield. Short channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage power. Double gate devices suppress SCEs and are potential candidates for replacing Bulk technology in nanometer nodes. Threshold voltage control in planar asymmetric double gate transistor (IGFET) using a fourth terminal provides an effective means of combating process variations and low power design. In this thesis, using various case studies, we analyzed the suitability of IGFET for variation control and low power design. We also performed an extensive comparison between IGFET and Bulk for reducing variability, improving yield and leakage power reduction using power gating. We also proposed a new circuit topology for IGFET, which on average shows 33.8 percent lower leakage and 34.9 percent lower area at the cost of 2.8 percent increase in total active mode power, for basic logic gates. Finally, we showed a technique for reducing leakage of minimum sized devices designed using new circuit topology for IGFET.

Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution under continuous solution space. However, it is more complex to use Lagrangian relaxation under discrete solution space. The Lagrangian dual problem is non-convex and previously a sub-gradient method was used to solve it. The sub-gradient method is a greedy approach for substituting gradient method in the deepest descent method, and has room for further improvement. In addition, Lagrangian sub-problem cannot be solved directly by mathematical approaches under discrete solution space. Here we propose a new Lagrangian relaxation-based method for simultaneous gate sizing and Vt assignment under discrete solution space. In this work, some new approaches are provided to solve the Lagrangian dual problem considering not only slack but also the relationship between Lagrangian multipliers and circuit timing. We want to solve the Lagrangian dual problem more precisely than did previous methods, such as the sub-gradient method. In addition, a table-lookup method is provided to replace mathematical approaches for solving the Lagrangian sub-problem under discrete size and Vt options. The experimental results show that our method can lead to about 50 percent and 58 percent power reduction subject to the same timing constraints compared with a Lagrangian relaxation method using sub-gradient method and a state-of-the-art previous work. These two methods are implemented by us for comparison. Our method also results in better circuit timing subject to tight timing constraints.

The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this thesis, we fabricate another new structure (asymmetry dual-gate TFTs).For asymmetry dual-gate TFTs, the ITO back gate is extended to the middle of the channel and only covered on the drain contact. The new structure has the advantages of dual-gate TFTs. With dual-channel conduction, it exhibit higher Ion and lower photo leakage current performance than the conventional inverted staggered TFTs. In addition, we use the asymmetry dual-gate structure to investigate how the parasitic capacitance influences the feed-through voltage by C-V measurement. We also to investigate the influences of electrical characteristics with the ITO back gate whether or not overlap the source contact. The asymmetry in on current with source-drain swapping can be attributed to the difference in the ITO back gate whether overlaps the source contact. Finally, it simulated the process of the degradation on the TFTs to find the stability mechanism of the TFTs.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 124-135). Available also in a digital version from Dissertation Abstracts.

Thesis (M. Sc.)--University of Alberta, 2009. / Title from PDF file main screen (viewed on Dec. 14, 2009). "A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science, Department of Electrical and Computer Engineering, University of Alberta." Includes bibliographical references.