For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

A good understanding of flow in a number of hydraulic structures, such as energy dissipators, among others, is needed to effectively control upstream and downstream flow conditions, for instance, high water depth and velocity to ensure, scouring, flow stability and control scouring, which is thus crucial to ensuring safe acceptable operation. Although some previous research exists on minimizing scouring and flow fluctuations after hydraulic structures, none of this research can fully resolve all issues of concern. In this research, three types of structures were studied, as follows: a) a vertical gate; b) a vertical gate with an expansion; and c) a vertical gate with a contraction. A Stability Concept was introduced and defined to characterize the conditions downstream of gated structures. When established criteria for stability are met, erosion is prevented. This research then investigated and evaluated two methods to classify the flow downstream of a gated vii structure to easily determine stability. The two classification methods are: the Flow Stability Factor and the Flow Stability Number. The Flow Stability Factor, which is developed based on the Fuzzy Concept, is defined in the range of 0 to 1; the maximum value is one and indicates that the flow is completely stable; and the minimum value is zero and indicates that the flow is completely unstable. The Flow Stability Number is defined as the ratio of total energy at two channel sections with a maximum value of one, and it allows flow conditions to be classified for various hydraulic structures; the number is dimensionless and quantitatively defines the flow stability downstream of a hydraulic structure under critical and subcritical flow conditions herein studied, also allowing for an estimate of the downstream stable condition for operation of a hydraulic structure. This research also implemented an Artificial Neural Network to determine the optimal gate opening that ensures a downstream stable condition. A post-processing method (regression-based) was also introduced to reduce the differences in the amount of the gate openings between experimental results and artificial intelligence estimates. The results indicate that the differences were reduced approximately 2% when the post-processing method was implemented on the Artificial Neural Network estimates. This method provides reasonable results when few data values are available and the Artificial Neural Network cannot be well trained. Experiments were conducted in two laboratories, for two different scales, to investigate any possible scale effect. Results indicate, for instance, that the case of the vertical gate with an expansion performs better in producing a downstream stable condition than the other two studied structures. Moreover, it was found that smaller changes caused by expansions and contractions on the channel width show better performance in ensuring a viii downstream stable condition in the cases of a vertical gate with an expansion and a vertical gate with a contraction over a wide range of structures. Moreover, upstream flow depths in the gate with expansion are higher than in the cases of a gate and a gate with a contraction, suggesting that it may be more appropriate for agriculture applications. This research also applied Game Theory and the Nash Equilibrium Concept in selecting the best choice among various structures, under different flow expectations. In addition, the accuracy of the Flow Stability Factor and the Flow Stability number were compared. This showed that the Flow Stability Factor and the Flow Stability number had good agreement in stable conditions. Hence, the Flow Stability Factor can then be used instead of the Flow Stability number to define stable conditions, as a visual method that does not need any measurement. Importantly, a Fuzzy-based Efficiency Index, a method based on an image processing technique, was also innovatively tested to estimate the hydraulic efficiency of the hydraulic structures. The method was tested and validated using laboratory data with an average agreement of 96.45%, and then demonstrated for prototype case situations in Florida and California. These cases yielded overall efficiencies of 96% and 97.87% in Spillway Park, FL and Oroville Dam, CA, respectively. Statistical assessment was also done on the image, determining an Efficiency Index. Specifically, an image histogram was extracted from the grayscale image, then the mean and standard deviation of the histogram was used to calculate the Index. The method uses the darkness and whiteness of the image to estimate the Efficiency Index; it is easy to use, quick, low cost, and trustworthy.

The project compares and describes the characteristics of optical and electromagnetic methods, used for measuring the object’s velocity. Some of these are used at the ballistic laboratory of PROTOTYPA, a.s. company. The rest is mentioned in order to increase the range of the project and are not engaged by the company. The practical part involves measuring and processing the magnetic fields of various appliances. There is a method and appliance designed to process the link between flying object and sensor.

Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / Some Telemetry systems today receive a binary phase shift keying modulation format. Typically, to demodulate BPSK requires using a carrier synchronizer followed by a bit synchronizer. Demodulation of BPSK can be accomplished using digital signal processing techniques to implement both synchronizers. This paper describes a digital system that demodulates a 16 KHZ, 2KBPS BPSK signal. In order to evaluate these techniques, the theory of operation was evaluated. Additionally, a computer simulation of the demodulator was developed. The computer simulation was implemented using Pascal. The techniques were optimized to give maximum performance while requiring minimum hardware and power in an actual implementation.

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