In this thesis, we propose a circuit design technique that reduces the energy utilized by any logic circuit for computation. We achieve this, by reducing the voltage swing on the circuit without greatly compromising the speed of operation and keeping in mind the noise margin constraints. Our technique involves the use of head or tail transistors that provide a Vth drop in the voltage swing. We choose to use head or tail transistors on alternate logic levels providing us with an option of driver stage, based on the noise margin of the subsequent stage. We demonstrate the working of this concept on inverter chains, to prove the correctness as well as the ability of the reduced voltage swing circuits to drive subsequent stages. We also discuss the implementation of this technique on basic gates and simple combinational circuits. We then show detailed experiments on a larger circuit, in this case a Kogge-Stone parallel prefix adder. We will discuss the overheads involved in the design and methods to partially overcome these by the use of selectively skewed gates and application of forward body bias. Finally we implement the same design using a different technology to demonstrate the scalability of the technique. / text

Student Number : 9709049J - MSc research report - School of Construction Economics and Management - Faculty of Engineering and the Built Environment / Spiralling violent crime in South Africa has led to the increased use of access control to restrict access to suburbs and thus make it more difficult to perpetrate violent crime against residents. This neighbourhood enclosure normally takes the form of booms, palisade fences and security guards to close off entire suburbs that were once or still are public property. This study examines the effect of the implementation of neighbourhood enclosure on property values. The primary methodology used to research this concentrated on the analysis of residential property values, bond approvals and relative amounts of property transferred within the period of late 2002 and mid 2004. Analysis was based on information available at the deed’s office. Limitations included the small sample size and the availability of information. Applicants for suburban closures can use the results of the study to verify or discredit claims of property value increases. Municipalities can match property values to services and rates. Results showed that property values that were found to be either similar in adjacent open and enclosed areas or more expensive in enclosed areas. The latter trend was evident in higher value properties. This illustrates a higher demand for properties in these enclosed areas than in the adjacent open areas. Further analysis of prices showed that, in all cases over the same period, prices increased by more in enclosed areas than in open areas. This statistic proves the hypothesis, that neighbourhood enclosure increases the value of properties within the enclosure when compared to similar properties in adjacent open areas. Analysis of the value of bonds granted in an area showed that banks appear to ignore the enclosure status of the immediate area.

Lorenzo Ghiberti's east door of the Baptistery of San Giovanni in Florence, long famed as the Gates of Paradise, displays Old Testament stories in sculptural relief on ten gilded bronze panels. Stressing the significance of the Gates of Paradise as a public monument imbedded in the fabric of Florentine society will enhance our understanding of the cultural use of the door within its built environment. Consideration of its context could in turn clarify the motivation behind the choices for the iconographical program. Previous studies of the Gates of Paradise tend to isolate each narrative panel rather than examining the Gates as one door made up of ten unified panels (including decorative framing). As a result, the Gates of Paradise have rarely been looked at in terms of architectural function or context. The approach of the present study focuses on the Gates of Paradise as a significant architectural feature of Florence's built environment, as a feature that functioned as a centerpiece for the Baptistery and the Cathedral complex, and as a setting for the many spectacles that took place in that environment. This investigation aims to define the inseparable religious and civic functioning of the Gates of Paradise and to identify connections between specific function and the iconographical program. The research examines in depth the imagery of the Gates of Paradise, scrutinizing the function of the Gates within its physical setting, in the ceremonies of baptism, and in the regular rituals of the Florentine liturgical calendar. This hitherto-unexamined analysis of the Florentine liturgical ritual utilizes Medieval and Renaissance service books such as the Ritus in ecclesia servandi, Mores et consuetudines canonice florentine, Missal Ms. Edili 107 (Biblioteca Medicea Laurenziana), and the Missale romanum Mediolani, 1474. The examination of the Gates' function offers illumination of the possible meaning(s) conveyed by the choice of biblical narratives that make up the program. Research suggests that the iconographical program for the Gates of Paradise connects predominantly to its major function as the principal ritual entrance for the Baptistery. The program reiterates the liturgy for the season leading up to the Church's traditional celebratory period of baptism and the baptismal liturgy. While most days throughout the year the south portal was used for the daily baptismal ceremony, this special baptism-related use of the Gates reinforce the liturgy of the season which teaches and emphasizes the significance of the sacrament of baptism and the role of the Church in salvation.

We present a design technique, called partial evaluation triple modular redundancy for hardening combinational circuits against Single Event Upsets (SEU). The input environment is given in terms of signal probabilities of the lines. This is useful information to determine the redundant gates of the given circuit. The basic ideas of partial redundancy and temporal triple modular redundancy are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. This technique fails in cases when the actual inputs to the circuit are not in accordance to the rounded logic values. In such cases the technique of temporal TMR is used. However, there is some overhead in this process because of the voter circuits and the need to choose the outputs computed by partially evaluated circuit and circuit using temporal TMR. For testing the circuit exhaustively against SEUs, a fault insertion simulator is used. This simulator introduces errors in the circuits during simulation which represent SEUs. This technique of partial evaluation redundancy is thoroughly tested on MCNC’91 benchmarks using Cadence NCLaunch simulator. By employing this technique, in most of the cases we can reduce the area overhead of the hardened circuit when compared with the traditional Triple Modular Redundancy (TMR). The improvement in area is based on the total number of gates and the actual number of outputs. For circuits with large number of gates and less number of outputs, there is greater savings in area. In some cases, the area overhead because of the proposed technique is greater than the traditional TMR. This usually occurs in smaller circuits or in circuits with more number of outputs.

Due to the low current ratings of the currently available silicon carbide (SiC) switches they cannot be employed in high-power converters. Thus, it is necessary to parallel-connect several switches in order to reach higher current ratings. This paper presents an investigation of parallel-connected normally-on SiC junction field effect transistors. There are four crucial parameters affecting the effectiveness of the parallel-connected switches. However, the pinch-off voltage and the reverse breakdown voltage of the gates seem to be the most important parameters which affect the switching performance of the devices. In particular, the spread in these two parameters might affect the stable off-state operation of the switches. The switching performance and the switching losses of a pair of parallel-connected devices having different reverse breakdown voltages of the gates is investigated by employing three different gate-driver configurations. It is experimentally shown that using a single gate-driver circuit the switching performance of the parallel-connected devices is almost identical, while the total switching losses are lower compared to the other two configurations. / <p>QC 20121116</p>

This thesis focuses on pioneering a scalable route to fabricate quantum information devices based upon single InAs/InP quantum dots emitting in the telecommunications wavelength band around 1550 nm. Using metallic gates in combination with nanotemplate, site-selective epitaxy techniques, arrays of single quantum dots are produced and electrostatically tuned with a high degree of control over the electrical and optical properties of each individual quantum dot. Using metallic gates to apply local electric fields, the number of electrons within each quantum dot can be tuned and the nature of the optical recombination process controlled. Four electrostatic gates mounted along the sides of a square-based, pyramidal nanotemplate in combination with a flat metallic gate on the back of the InP substrate allow the application of electric fields in any direction across a single quantum dot. Using lateral fields provided by the metallic gates on the sidewalls of the pyramid and a vertical electric field able to control the charge state of the quantum dot, the exchange splitting of the exciton, trion and biexciton are measured as a function of gate voltage. A quadrupole electric field configuration is predicted to symmetrize the product of electron and hole wavefunctions within the dot, producing two degenerate exciton states from the two possible optical decay pathways of the biexciton. Building upon these capabilities, the anisotropic exchange splitting between the exciton states within the biexciton cascade is shown to be reversibly tuned through zero for the first time. We show direct control over the electron and hole wavefunction symmetry, thus enabling the entanglement of emitted photon pairs in asymmetric quantum dots. Optical spectroscopy of single InAs/InP quantum dots atop pyramidal nanotemplates in magnetic fields up to 28T is used to examine the dispersion of the s, p and d shell states. The g-factor and diamagnetic shift of the exciton and charged exciton states from over thirty single quantum dots are calculated from the spectra. The g-factor shows a generally linear dependence on dot emission energy, in agreement with previous work on this subject. A positive linear correlation between diamagnetic coefficient and g-factor is observed.

Vi har alltsedan våra praktikperioder haft en grundläggande förståelse för hur mankan arbeta inom organisationer där innovation är ett centralt begrepp. Vi har dockaldrig kommit i kontakt med beslutsprocesserna runt dessa projekt. Efter praktikenhar vi ifrågasatt de värderingsmetoder som vi tidigare sett som relativt heltäckande.Vi är båda aktiva på börsen vilket är ytterligare en faktor som ökat vårt intresse förämnet då börsens värdering av bolag med hög risk och hög innovationshöjd ärosäker. Där saknas analyser som belyser problemet. Detta har lett till att vi söktvärderingar på dessa bolag med hjälp av olika metoder och ökat förståelsen för hurextern värdering går till.Författarnas studier har naturligtvis inspirerat valet av uppsatsämne. Studierna harockså påverkat hur vi ser på värdering och vilka resultat vi förväntar oss av studien.Vi har läst finansiering där värdering är väldigt centralt eftersom det är viktigt att sättamöjligheter i relation till varandra. Här har vi under hösten berört flera metoder där deflesta är baserade på diskonterade kassaflöden. Den andra parametern förutomkassaflöden är risken. Eftersom risk och avkastning alltid ska följa varandra så måsteavkastningen vara hög nog för risknivån. Risken har vi beräknat med hjälp av CAPMeller WACC. Dessa metoder använder sig av antingen marknadsförhållanden ellermer specifika förhållanden inom bolaget för att mäta risken. Vi har också kommit ikontakt med BASEL-fördragen och därmed Value-at-Riskmåtten som beräknar hurmycket man riskerar att förlora under en viss tid med en specificerad säkerhet. Medhjälp av dessa metoder och genom att jämföra nyckeltal har vi värderat allt frånprojekt till portföljer. Vi har alltid haft kassaflöden som grund för beräkningarna dockmed osäkerhet kring omfattningen av dessa.Under våra praktikperioder så arbetade vi båda två i väldigt innovativa miljöer. Ingenav oss kom i direktkontakt med beslutsprocessen då man valde mellan projekt, menett intresse för hur det gick till föddes. Bristen på förklaringar hur man hanteradeprojekt utan säkra kassaflöden under vår utbildning och även i de rapporter vi läst harbara ökat vårt intresse kring företag och deras projektval.Eftersom vi vill sätta oss in i hur beslutsprocessen ser ut på innovativa företag har vivalt en abduktiv metod, dvs. att utgå från vår data och teori för att utforska ettforskningsgap. Vår förhoppning är att den här studien kan vara en inspirationskälla tillandra abduktiva eller induktiva studier liksom vara en grund för vidare deduktivforskning i ämnet.Vi vill också passa på att tacka de medverkande företagen och personerna viintervjuat. Vi vill också rikta ett tack till vår handledare Anders Isaksson för all hjälpgenom denna snåriga process.

This thesis focuses on pioneering a scalable route to fabricate quantum information devices based upon single InAs/InP quantum dots emitting in the telecommunications wavelength band around 1550 nm. Using metallic gates in combination with nanotemplate, site-selective epitaxy techniques, arrays of single quantum dots are produced and electrostatically tuned with a high degree of control over the electrical and optical properties of each individual quantum dot. Using metallic gates to apply local electric fields, the number of electrons within each quantum dot can be tuned and the nature of the optical recombination process controlled. Four electrostatic gates mounted along the sides of a square-based, pyramidal nanotemplate in combination with a flat metallic gate on the back of the InP substrate allow the application of electric fields in any direction across a single quantum dot. Using lateral fields provided by the metallic gates on the sidewalls of the pyramid and a vertical electric field able to control the charge state of the quantum dot, the exchange splitting of the exciton, trion and biexciton are measured as a function of gate voltage. A quadrupole electric field configuration is predicted to symmetrize the product of electron and hole wavefunctions within the dot, producing two degenerate exciton states from the two possible optical decay pathways of the biexciton. Building upon these capabilities, the anisotropic exchange splitting between the exciton states within the biexciton cascade is shown to be reversibly tuned through zero for the first time. We show direct control over the electron and hole wavefunction symmetry, thus enabling the entanglement of emitted photon pairs in asymmetric quantum dots. Optical spectroscopy of single InAs/InP quantum dots atop pyramidal nanotemplates in magnetic fields up to 28T is used to examine the dispersion of the s, p and d shell states. The g-factor and diamagnetic shift of the exciton and charged exciton states from over thirty single quantum dots are calculated from the spectra. The g-factor shows a generally linear dependence on dot emission energy, in agreement with previous work on this subject. A positive linear correlation between diamagnetic coefficient and g-factor is observed.

Thesis (M.A.)--Brigham Young University. Dept. of English, 1998. / Includes bibliographical references (p. 129-132).

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.