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Over the last four decades the integrated circuit industry has evolved in a tremendous pace. This success has been driven by the scaling of device sizes leading to higher and higher integration capability, which have enabled more functionality and higher performance. The impressive evolution of modern high-performance microprocessors have resulted in chips with over a billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, scaling of device sizes is still predicted to continue at least into the near future. However, there are a number of challenges to overcome to be able to continue the increase of integration at the same pace. Three of the major challenges are increasing power dissipation due to clocking of synchronous circuit, increasing leakage currents causing growing static power dissipation and reduced circuit robustness, and finally increasing spread in circuit parameters due to physical limitations in the manufacturing process. This thesis presents a number of circuit techniques that aims to help in all three of the mentioned challenges.Power dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation for multi-GHz systems. As the complexity and size of synchronous systems continues to increase, clock power will also increase. This makes novel power reduction techniques absolutely crucial in future VLSI design. In this thesis an energy recovering clocking technique aimed at reducing the total chip clock power is presented. Based on theoretical analysis the technique is shown to enable considerable clock power savings. Moreover, the impact of the proposed technique on conventional flip-flop topologies is studied. Measurements on an experimental chip design proves the technique, and shows more than 56% lower clock power compared to conventional clock distribution techniques at clock frequencies up to 1.76 GHz.Static leakage power dissipation is a considerable contributor to the total power dissipation. This power is dissipated even for circuits that are idle and not contributing to the operation. Hence, with increasing number of transistors on each chip, circuit techniques which reduce the static leakage currents are necessary. In this thesis a technique is discussed which reduces the static leakage current in a microcode ROM resulting in 30% reduction of the leakage power with no area or performance penalty.Apart from increasing static power dissipation the increasing leakage currents also impact the robustness constraints of the circuits. This is important for regenerative circuits like flip-flops and latches where a changed state due to leakage will lead to loss of functionality. This is a serious issue especially for high-performance dynamic circuits, which are attractive in order to limit the clock load in the design. However, with the increasing leakage the robustness of dynamic circuits reduces dramatically. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops, a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique, which is implemented on a reconfigurable flip-flop. At normal clock frequencies the flip-flop is configured in dynamic mode, and reduces the clock power by 25% due to the lower clock load. During any low-frequency operation, the flip-flop is configured as a static flip-flop retaining full functional robustness.As scaling continues further towards the fundamental atomistic limits, several challenges arise for continuing industrial device integration. Large inaccuracies in lithography process, impurities in manufacturing, and reduced control of dopant levels during implantation all cause increasing statistical spread of performance, power, and robustness of the devices. In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.

Dans le cadre des communications numériques sans fil, la vitesse d'échange de données (débit) reste toujours une des caractéristiques qui limite la performance du système. Une diminution des temps d¿échange est donc nécessaire pour l'amélioration de la performance et l'introduction des nouvelles applications. Des applications comme " Wireless HD " rendent possible la transmission sans fil de vidéo non-compressée " à haute définition (débit = 4 Gbps) " Kiosk Downloading " permettrait l'échange de données à haut débit (1-2 Gbps) sur une courte portée (1 -2 mts). Pour atteindre ce débit, la bande autour de 60 GHz est donc visée pour profiter de ses 7 GHz de bande passante disponibles. Dans le cadre du projet PANAMA, un intérêt spécial est aussi donné à l'efficacité du système transmetteur (Amplificateur de Puissance et Antenne) et ce sera donc un autre axe de notre recherche : l'étude des stratégies pour l'amélioration du rendement énergétique global. On se concentrera surtout sur la connexion PA ' Antenne qui donnera lieu aux stratégies de co-intégration et de co-conception. Plusieurs problématiques doivent être confrontées : la co-simulation (actif et passif) ainsi que la mesure des antennes dans cette bande millimétrique. Cette haute fréquence introduit des limitations, notamment sur les performances de l'antenne. Ainsi le but de cette thèse est de proposer des solutions d'antennes qui remplissent les besoins de l'application (solutions basée sur le résonateur diélectrique). La solution complète des systèmes intégrés doit comprendre également des solutions encapsulées ( "packaged " ), sujet aussi abordé dans ce travail.

In this thesis, based on the indoor channel measurements and ray-tracing modeling for the indoor mm-wave wireless communications, the challenges of the design of the radio in this band is studied. Considering the recently developed standards such as IEEE 802.15.3c, ECMA and WiGig at 60 GHz, the link budget of the system design for different classes of operation is done and the requirement for the antenna and other RF sections are extracted. Based on radiation characteristics of mm-wave and the fundamental limits of low-cost Silicon technology, it is shown that phased-array is the ultimate solution for the radio and physical layer of the mobile millimeter wave multi-Gb/s wireless networks. Different phased-array configurations are studied and a low-cost single-receiver array architecture with RF phase-shifting is proposed. A systematic approach to the analysis of the overall noise-figure of the proposed architecture is presented and the component technical requirements are derived for the system level specifications. The proposed on-chip antennas and antenna-in-packages for various applications are designed and verified by the measurement results. The design of patch antennas on the low-cost RT/Duroid substrate and the slot antennas on the IPD technologies as well as the compact on-chip slot DRA antenna are explained in the antenna design section. The design of reflective-type phase shifters in CMOS and MEMS technologies is explained. Finally, the design details of two developed 60 GHz integrated phased-arrays in CMOS technology are discussed. Front-end circuit blocks such as LNA, continuous passive reflective-type phase shifters, power combiner and variable gain amplifiers are investigated, designed and developed for a 60 GHz phased-array radio in CMOS technology. In the first design, the two-element CMOS phased-array front-ends based on passive phase shifting architecture is proposed and developed. In the second phased-array, the recently developed on-chip dielectric resonator antenna in our group in lower frequency is scaled and integrated with the front-end.

In modern telecommunication there is the demand of high data rates using wideband component design. FCC has introduced the UWB spectrum for high speed data communication. UWB systems have attracted the attention of researchers.  Six-port transmitters and receivers are strong candidates for UWB systems and research is being done on six-port modulators and demodulators. In this work an effort is made to compare the performance of conventional single-ended six-port transmitter and receiver with differential six-port transmitters and receivers.    In this thesis, single ended and differential six-port correlators are designed on 7.5 GHz using Agilent Inc. EDA tool ADS and their performance is evaluated. A new wide-band differential six-port correlator is implemented using rat-race couplers and double-sided parallel strip-line phase inverter. The designed six-port correlators are used for 8-PSK modulation and demodulation. For transmitter-receiver system, mixed analog-DSP designing is used. The integral components of the system are evaluated individually and behavioral modeling is used to evaluate the complete transmitter-receiver system. The single-ended and differential systems are evaluated for noise-figure, dynamic range, bit error rate and data rate.

The objective of the proposed research is to present a compact system-on-package (SOP)-based passive front-end solution for millimeter-wave wireless communication/sensor applications, that consists of fully integrated three dimensional (3D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication and testing of V-band transceiver front-end modules using multilayer low temperature co-fired (LTCC) technology. The millimeter-wave front-end module is the foundation of 60 GHz (V-band) wireless systems for short-range multimedia applications, such as high-speed internet access, video streaming and content download. Its integration poses stringent challenges in terms of high performance, large number of embedded passive components, low power consumption, low interference between integrated components and compactness. To overcome these major challenges, a high level of integration of embedded passive functions using low-cost and high-performance materials that can be laminated in 3D, such as the multilayer LTCC, is significantly critical in the module-level design. In this work, various compact and high-performance passive building blocks have been developed in both microstrip and cavity configurations and their integration, enabling a complete passives integration solution for 3D low-cost wireless millimeter-wave front-end modules. It is worthy to note that most of the designs implemented comes away with novel ideas and is presented as the first extensive state-of-art components, entirely validated by measured data at 60 GHz bands.

Les télécommunications sans fil connaissent un intérêt toujours soutenu depuis plus d'une décennie car elles permettent une simplification des infrastructures par rapport aux télécommunications filaires, une mobilité accrue des terminaux, et finalement un usage plus souple pour l'utilisateur.<br /><br />Le défi actuel de ce champ des télécommunications est d'assurer une augmentation des débits de transmission. Pour cela plusieurs techniques sont envisagées, parmi lesquelles la montée en fréquence vers le spectre des ondes millimétriques. Cette approche est à la base de cette thèse qui présente les résultats de la caractérisation et de la modélisation statistique du canal de propagation intra-bâtiment à 60 GHz. Ces travaux sont basés sur plusieurs campagnes de mesure menées principalement en milieu résidentiel.<br /><br />Les principaux résultats soulignent l'importance du problème d'obstruction provoqué par l'activité humaine, ainsi que la difficulté de la propagation entre les pièces d'un bâtiment. Enfin, ces mesures révèlent que la mise en œuvre d'une diversité angulaire au sein du réseau devrait permettre de contrer ces deux difficultés. Par ailleurs, sont proposés des modèles de la propagation spatio-temporel et variant dans le temps, basés sur les propriétés statistiques des différentes caractéristiques du canal.

La bande de fréquences au voisinage de 60GHz (bande 57-64GHz) est en développement rapide pour les systèmes de communication sans fil à courte portée. Cependant, les rayonnements autour de 60GHz sont absents du spectre naturel et les organismes vivants n'y ont encore jamais été exposés dans les conditions environnementales. <br />Ce travail de thèse porte sur l'analyse des effets potentiels des rayonnements millimétriques de faible puissance au niveau cellulaire. Les études sont axées sur deux directions de recherche. Premièrement, nous avons considéré l'influence des ondes millimétriques à 60GHz sur la structure et les propriétés biophysiques des modèles artificiels des membranes biologiques. Deuxièmement, nous avons étudié l'influence du rayonnement millimétrique autour de 60GHz sur les modifications de l'expression génétique des protéines chaperones dans les cellules gliales du cerveau humain.

This thesis addresses the design study, implementation and analysis of signal processing algorithms for a 79 GHz millimeter-wave Phase Modulated Continuous Wave (PMCW) Multi Input Multi Output (MIMO) short range radar; performed in IMEC research institute (Leuven, Belgium). The radar system targets high resolution performance with low power consumption in order to integrate a full MIMO radar transceiver with digital processor and antennas in a compact package featuring a size of 1 cm2. Achieving such radar system characteristics requires the exploitation of a highly demanding digital architecture with signal processing gain and high range, speed and angle resolutions. The improved resolution and detection capabilities will be achieved by performing signal processing algorithms on the reflected waveform. The digital front-end implements parallel range gate processing with a bank of correlators that perform: pulse compression, coherent accumulation to further increase Signal to Noise Ratio (SNR) and N-point FFT to extract the Doppler information. The use of MIMO is proposed implementing a code domain technique in the PMCW waveform, the Outer Hadamard Code MIMO. This concept makes use of a unique sequence for all the transmitting antennas that is rendered by an outer sequence to ensure the orthogonality of the transmitted waveforms. The outer code makes use of the good cross-correlation properties of the Hadamard sequences and the waveform uses sequences that exhibit perfect auto-correlation profile, the Almost Perfect Autocorrelation Sequences (APAS). The MIMO implementation results in higher angular resolution and extra processing gain. The use of beamforming techniques in the radar allows the angle estimation of the detected targets; using rough and fine beamforming that provides with coarse and precise Angle of Arrival (AoA) estimation in an early and late stage respectively. A Constant False Alarm Rate (CFAR) processing stage is implemented in the stage of the system where higher signal processing gain is achieved. This algorithm allows the variation of the CFAR parameters and analyzes the detections in order to improve the probability of detection (Pd) while decreasing the probability of false alarm (Pfa). A series of simulations with different scenarios and variable parameters are set in order to analyze the performance of the system. The simulations analyze the gain achieved in each stage and their outcomes show an impressive processing gain that can reach SNR improvements as high as 77 dB for a small virtual array while keeping the Pfa low with the CFAR adjustment. The use of bigger arrays demonstrates the possibility to enable clear detections for low Radar Cross Section (RCS) targets in far distances of the unambiguous range. The use of beamforming shows interference reduction improvement as the beam widths narrow with the increasing number of virtual array antennas. These results have been achieved while keeping the system design parameters to a range resolution of 7.5 cm for a maximum range of 37.5 meters with speed resolution of 0.2 m/s and a maximum detectable speed of 12.66 m/s. The outcomes support the good performance of the signal processing techniques implemented and the benefits in applying them in a SoC mmWave MIMO radar.

This thesis describes fundamental approaches to quantify rate versus power consumption tradeoffs for cascaded communication systems. The discussion is bolstered by a large number of in-situ channel measurements, which are used in discussions of the power consumption of future massively broadband cellular systems. Chapter one provides an introduction. Chapter two discusses power consumption trends in modern communication systems. Chapter three introduces the consumption factor framework. Chapter four discusses the channel measurement campaign. Chapter five concludes the thesis, and uses the measurement results to estimate power consumption and capacity of future cellular systems. In addition, chapter five extends the consumption factor theory and draws fundamental conclusions about the energy price per bit for a general cascaded communication system. / text