The field buses, and particularly the ‘PROFIBUS’, are currently widely used in automation systems, with the intention to automate industrial applications. It is of the utmost importance that one should understand how these systems operate, because failure to understand may result in improper applications, which can ultimately lead to intense network problems and, consequently, lead to potential catastrophic failures in industrial equipment, as well as compromising the health and safety of the people. This research was the performance evaluation of SAMANCOR PROFIBUS network that controls the chrome manufacturing plant. The problem with the network was that it was failing intermittently. These network failures resulted in loss of production, loss of throughput, compromised quality, downtime due to reworks, high costs in energy used to rework, and equipment damage or failure. One of the OBJECTIVES of the research was to carry out a performance evaluation of the PROFIBUS network in terms of the possible electromagnetic interference (EMI) within the plant’s PLC network. This topic emanated from the network service providers that kept insisting that the network was unstable, due to possible electromagnetic interference caused by possible high voltage cables running next to the plant network cables. This assumption was without fact, and hence the research was conducted. The QUANTITATIVE research method was used to conduct the research, where simulation of the plant network, using external parameters, were used to carry out the research. Furthermore, experiments were conducted and the physical measurements were performed on the network, where parameters derived from these measurements were used to compare the two networks. In essence, the network was tested under known configurations. The manner in which the network was simulated was that of stepping up the electrical current from the external device, and recording the response of the network. A stand-alone network rig was built and used to carry out the tests, and the results were compared with those obtained from the plant network. / Electrical and Mining Engineering / M. Tech. (Electrical Engineering)

Les applications grand public comme la téléphonie mobile ou les cartes bancaires manipulent des données confidentielles. A ce titre, les circuits qui les composent font de plus en plus l'objet d'attaques qui présentent des menaces pour la sécurité des données. Les concepteurs de systèmes sur puce (SoC) doivent donc proposer des solutions sécurisées, tout en limitant le coût et la complexité globale des applications. L’analyse des attaques existantes sur les circuits numériques nous a orienté vers celles se basant sur la tension d'alimentation, dans des nœuds technologiques avancés.Dans un premier temps, nous avons déterminé la signature électrique d’un circuit en phase de conception. Pour cela, un modèle électrique a été proposé, prenant en compte la consommation en courant et la capacité de la grille d'alimentation. L'extraction de ces paramètres ainsi que l'évaluation du modèle sont présentées. L’utilisation de ce modèle a permis de mesurer la vulnérabilité d’un circuit mais aussi d’évaluer quantitativement des contremesures, notamment celle utilisant des capacités de découplage. Ensuite, l’étude se consacre à l’injection de fautes par impulsions de tension d’alimentation. Les mécanismes d’injection de fautes sur des circuits numériques ont été étudiés. Dès lors, des solutions de détection d’attaques ont été proposées et évaluées à la fois en simulation et par des tests électriques sur circuit. Les résultats ont permis de confirmer les analyses théoriques et la méthodologie utilisée.Ce travail a ainsi montré la faisabilité de solutions à bas coût contre les attaques actives et passives en tension, utilisables dans le cadre d’un développement industriel de produits. / General use products as mobile phones or smartcards manipulate confidential data. As such, the circuits composing them are more and more prone to physical attacks, which involve a threat for their security. As a result, SoC designers have to develop efficient countermeasures without increasing overall cost and complexity of the final application. The analysis of existing attacks on digital circuits leads to consider power attacks, in advanced technology nodes.First of all, the power signature of a circuit was determined at design time. To do so, an electrical model was suggested based on the current consumption and the overall power grid capacitance. The methodology to extract these parameters, as well as the evaluation of the model are presented. This model allows designers to anticipate information leakage at design time and to quantify the protection of countermeasures, as the use of integrated decoupling capacitors. Then, the study was dedicated to power glitch attacks. The different fault injection mechanisms were analyzed in details. From then on, a set of detection circuits were suggested and evaluated at design time and on silicon by electrical tests. Both the theoretical analysis and the given methodology were confirmed by the test campaigns.This work demonstrated that the design of low-cost solutions against passive and active power attacks can be achieved, and used in a large scale product development.

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